The Design Of Charge Pump Phase Locked Loop For 433/915MHz Band

Thanks to the rapid development of semiconductor technology and communication technology in the past decade,various short-range wireless communication electronic products have poured into all aspects of modern society.The Tire Pressure Monitoring System,which is placed in cars,monitors the tire pressure and temperature in real-time through short-range wireless transmission technology to ensure vehicle safety.The core of the Tire Pressure Monitoring System is the radio frequency front-end wireless transceiver chip,and the phase-locked loop is a key component module with large complexity in the frequency synthesizer of the RF chip,which guarantees the spectrum purity of the output signal.The quality of the local oscillator signal provided by the phase-locked loop directly determines the communication performance of the entire system.In response to the challenges faced by the cost and reliability,etc of the actual project,with the support of the radio frequency project of Hunan Jinxin Electronics Technology Co.,Ltd.,this thesis mainly studies the structure of the phase-locked loop and completes the design of a charge pump phase-locked loop which is used to support the two frequency bands of 433 MHz and 915 MHz in the RF chip.This thesis first introduces the structure and working principle of the radio frequency front-end wireless transceiver chip,then starts from top to bottom,analyzes the structure of the charge pump phase locked loop according to the correlation theory gradually,discusses the frequency characteristics,noise characteristics and non-ideal effects,etc in the loop.According to the requirements of the project,design the loop parameters and implement each circuit module.In order to meet the high signal resolution,three different phase-locked loops are designed to work in conjunction;digital control modules are combined to design the new LC voltage-controlled oscillator and the new ring oscillator based on traditional circuits to improve frequency characteristics,reduce noise,improve linearity and increase the frequency tuning range;based on the structure of the traditional divide-by-2 frequency divider,a new currentmode logic high speed divide-by-2 frequency divider with high frequency and full swing output is designed;according to the loop locking time and the index requirements,design and optimize the passive third-order loop filter,the charge pump and the phase frequency detector circuit module,etc.Based on the standard CMOS process of SMIC 0.18?m 1P4 M,the circuit design was completed in the Cadence software under the Linux system,the Virtuoso software was used for layout design,the parasitic parameters were extracted in the Calibre software,and the post simulation of the phase locked loop was completed in Spectre RF.Results of the post simulation show: the loop locking time is about 80?s,and the time required for relocking after frequency hopping is about 55?s.When the phaselocked loop is operating in the 433 MHz frequency band,the tuning range is 721.348~1025.82 MHz,and the phase noise is about-80dBc/Hz@1MHz within the tuning range,the frequency resolution is 55.55 kHz,and the total static current consumption is about 18.4mA;when the phase-locked loop is operating in the 915 MHz frequency band,the tuning range is 1700.764~2237.508 MHz,and the phase noise is about-117dBc/Hz@1MHz within the tuning range,the frequency resolution is 52.6kHz,and the total static current consumption is about 20.7mA.The simulation results show that the design satisfies the system requirements and the test results verify the rationality of the design.