Adjustable Frequency Low Power Of Charge Pump Phase-locked Lop

Put forward higher requirements for wireless communication devices.Emerging devices promote the development of wireless communication integrated circuits towards high performance,miniaturization,and low power consumption.Phase locked loop(PLL),as an important module of wireless communication system,realizes its low power consumption and wide frequency range output at high frequency,which has become one of the hot spots of PLL research.In order to meet the requirements of multi-output frequency and low power consumption at high frequency for the phase-locked loop applied to system-on-a-chip(SoC),a low-power charge pump phase-locked with adjustable frequency was designed.First of all,in the overall structure design,the frequency discriminator uses a pre-charged frequency discriminator,the voltage-controlled oscillator uses a two-stage pseudo-differential ring oscillator,and the frequency divider module uses a single true flip-flop with no static power consumption.(True Single Phase Clock,TSPC)to meet the design requirements of low power consumption.Secondly,the voltage-controlled oscillator uses a voltage-controlled capacitor to adjust the frequency,which further reduces the power consumption during the dynamic locking process of the circuit,and realizes the expansion of the tuning curve by means of a digitally controlled tail current source to ensure a wider output frequency range.Then,in the design of the charge pump,a common-mode detection circuit is used to suppress the quiescent current mismatch,and a differential complementary switch is used to suppress the non-ideal effect of the charge pump in dynamic operation,thereby reducing the small reference spur of the output frequency.Finally,a programmable multi-mode prescaler structure is used to achieve a wider output frequency range,and the stability of the overall loop is verified by transfer function derivation and simulation.Based on the TSMC 40nm process,the design and verification of the overall circuit and layout are completed.The simulation results show that when the reference input frequency is 40MHz,the output frequency range of the VCO is 2.45GHz-5.2GHz,the output frequency range of the overall circuit is 2.56GHz-4.96GHz,and the circuit stabilization time is less than 2.2μs.At 4GHz,the phase noise is-89.1dBc/Hz@1MHz,the integrated jitter is 2.42ps,the reference spur is 66.5dB,the optimal FoM of the circuit is 232.1dB,the maximum power consumption is 1.44mW,and the overall layout area is 115μm×61 μm.