Research And Design Of Charge Pump Phase Locked Loop Based On Ring Oscillator

With the development of integrated circuits,frequency synthesis technology has also penetrated into all aspects of national life,science and technology.Common frequency synthesis techniques are direct frequency synthesis,phase-locked loop(PLL)frequency synthesis,direct digital synthesis.Compared with other frequency synthesis techniques,the PLL synthesizer has the characteristics of high output frequency,small phase noise and simple circuit structure.In many low noise applications,phase-locked loop is still indispensable.Therefore,the research and design of PLL still have high research value and commercial value.A charge pump phase-locked loop(CPPLL)is implemented in SMIC 0.13?mRF CMOS technology.THE reference frequency of the PLL is 10 MHz,which generates a 500MHz~800MHz clock with low jitter.The root mean square jitter of the output clock is less than 5ps.In circuit design,in order to generate a 4 symmetrical output in phase frequency detector,a latch structure is introduced to speed up the waveform flipping,which reduces the reference spurs working with charge pump.Based on the source-switching structure,a replica branch and a high gain operational amplifier are added to achieve a high-resolution current,of which mismatch is less than-144 pA.A Dummy switch is implemented to minimize the transient mismatch.A ring voltage-controlled oscillator with low phase noise is designed.This ring consists of three identical pseudo differential delay cell with PMOS input pair and NMOS load.A cross-coupled pair is also added to enlarge the swing and the slope of output,the phase noise of the ring is less than-110.6dBc/Hz at 1MHz offset frequency.The programmable divider whose divider ratio is 28~131 consists of a 4/5 prescaler,a pulse counter and a swallow counter.The post-simulation results show that CPPLL is performed well in all process corners.In tt process corner,the total power consumption is less than 25 mW and the lock time is less than 40?s.While operation frequency at 500 MHz and 800 MHz,the root mean square jitter are 3.53 ps and 3.36 ps,respectively.The PLL occupies a chip layout area of 453.41?m ×194.3?m.