Low-power Charge Pump Phase-locked Loop Circuit Design Based On 0.18?m CMOS Process

The phase-locked loop circuit is a feedback system capable of comparing the input reference frequency with the output feedback frequency,and can output a stable fundamental frequency signal which can be widely used in the modem system of the synchronous digital system and the communication system.Such as generating a local oscillator signal at the front end of the satellite navigation receiver.When the wireless communication module uses the charge pump phase-locked loop as the base frequency signal,the center frequency is generally up to 1GHz and above,in the high frequency environment,with the frequency increase system dynamic power consumption also increases,thus achieving low power consumption become the current Research hot spots at high frequencies.In this paper,TSMC 0.18?m CMOS process,using Cadence software designed a low-power charge pump phase-locked loop.The phase-locked loop includes frequency discriminator,charge pump,loop filter,voltage controlled oscillator,divider five sub-modules.The frequency discriminator mainly uses the tri-state structure D flip-flop and through the method of adjusting the delay unit,the phase dead zone problem is solved.Through the improved charge pump circuit,the charge sharing effect and current mismatch problem are effectively suppressed,while the number of MOS tube is reduced by nearly half,compared with the traditional carrier charge pump circuit,reducing the circuit power consumption and layout area.Charge pump phase-locked loop overall simulation shows that:power supply voltage 1.8V,charge pump phase-locked loop center frequency of 1GHz,Output frequency range of 908MHz~1.142GH,the input reference frequency of 100MHz,the lock time is 6.019?s,the output voltage fluctuation of 29.97mV,power consumption of 5.7mW,the overall layout area of0.065mm~2,and through the DRC and LVS.