Design Of Critical Circuit Of CDR For High-speed Serial RapidIO Interface

In the high-speed serial RapidIO data communication, as an opening interconnect protocol standards which based on reliability, RapidIO features in its high efficiency, excellent stability and low system cost, which provides a smart data transmission solution with high-bandwidth and low-latency for the communication between devices in systems. Considering the various non-ideal factors including the clock jitter, skew, queue synchronization and crosstalk noise, and along with the hardware cost, it generally transmits data signals instead of clock signals which synchronized with the data signal. In order to ensure the data synchronization problems of the receiver, we employ the clock and date recovery circuit (CDR) technology.The paper based on the interpretation of RapidIo interconnect architecture, with regard to the performance requirements of CDR, successfully explored critical circuit of CDR with the 0.13um CMOS technology, which is mainly applied to the high-speed serial RapidIO.The major contents and highlights of the research are as follows:(1) Through the study and comparison of several different kinds of CDR, and with consideration of the maximum design limits of speed, jitter and stability , The paper employ a CDR which based on PLL structure , combined with phase select interpolation technology and multi-phase technology to realize the clock signal recovery.(2) Taking stability and speed into account, we bettered the design of charge pump and voltage controlled oscillator, thereby the dead-region of FD and the non-ideal characteristics of common charge pump would get a preferable solution, and get through the Hspice simulate verification.(3) With in-depth research on the multiphase clock generation mechanism, design an oscillator which based on single-ended ring structure, nesting the VCO which has the three-grade structure and five-grade structure into loop structure, so as to achieve a clock signal with eight-phase equal phase difference ,whose adjacent phase difference isπ/4.(4) obey the high-speed digital hybrid circuit layout guidelines, realizing the layout design of the core CDR modules. The simulation results of circuit well satisfy the demands of the serial RapidIo interconnect architecture transmission requirements.