16-Bit High-resolution Analog-to-digital Converter For Radar System

With the increasing demand for high-resolution and high-bandwidth performance in communication systems,high-performance data converters have been widely used.In applications that require high-resolution,medium-speed ADCs,such as active phased array radar systems,precision instruments,etc.,Pipeline successive approximation analog-to-digital converters(Pipeline-SAR ADCs)have been widely used,owing to the structural characteristics of high speed and low power consumption,excellent features such as good compatibility with advanced CMOS technology.Facing to the application scenarios of single-channel high-precision and medium-speed ADCs in radar systems,a 16 Bit hybrid Two-Step Pipeline-ISDM-SAR ADC architecture that meets high-precision and medium-speed requirements based on the first-order incremental sigma-delta modulator(ISDM)is proposed in this thesis.The theoretical model is built based on Matlab.The first stage is a 7-bit SAR ADC containing a large DAC and a small DAC;the second stage is a 9-Bit SAR ADC and 3-Bit ISDM(1Bit Over Range),which achieves 11 bit conversion totally.The combination of two-step pipeline SAR ADC and low-noise ISDM,together with background comparator offset calibration,can make full use of the pipeline-timing advantages without sacrificing additional hardware overhead to achieve higher signal-to-noise ratio and energy efficiency.Compared with the traditional pipelined SAR ADC,the coarse quantization SAR ADC and a fine quantization ISDM in the second stage can not only better suppress the quantization noise of the second stage during the conversion,but also can reduce the comparator resolution requirements with the given power consumption.The inter-stage amplifier adopts Gainboost operation structure and provides 32 times closed-loop gain,while setting 2 Bit inter-stage redundancy to tolerate the influence of non-ideal factors of the whole ADC.In addition,a digital code integration circuit and a global clock generation circuit are designed to ensure the integrity of the entire Pipeline-ISDM-SAR ADC design.The specific circuit and layout are designed based on the TSMC 40nm-LP CMOS process.Under the conditions of 1.2V/1.8V supply voltage,TT process corner,27? and 33.3MS/s sampling rate with a-0.4dBFS@16MHz single-tone sinusoidal signal,post-layout simulation results show that the proposed hybrid ADC architecture can achieve a signal-to-noise and distortion ratio(SNDR)and a spurious-free dynamic range(SFDR)of 86.3dB and 102.5dBc respectively,with differential nonlinearity(DNL)and integral nonlinearity(INL)no more than 0.8LSB and 1.4LSB.The total power consumption of it is19.2m W.Therefore,the proposed hybrid Two-Step Pipeline-ISDM-SAR ADC architecture in this thesis has a potential application prospect in radar system or other high-precision analog-to-digital conversion scenarios.