Research Of Key Circuits In High-speed High-precision Pipelined ADC

Nowadays,wireless communication technology is developing rapidly,and 5G communication technology is gradually becoming popular,the requirements for information in terms of quality,quantity and speed are greatly increased,and signal processing is gradually developing in the direction of digitalization.Analog to Digital Convertor(ADC),as a key device to connect the real world and electronic devices,has higher and higher performance requirements,which has prompted ADCs to continuously update,improve and iterate,and the main direction of its development is high accuracy,high speed and low power consumption.Compared with other ADCs,pipelined ADCs can achieve a better compromise in speed,power consumption and accuracy,and have become the preferred structure for high-speed and high-precision ADC applications.As the key circuit of pipelined ADCs,especially pipelined Sub-ADCs,the performance of comparator in terms of speed,accuracy,and offset voltage is crucial to the performance of the whole module.Therefore,it is very important to design a comparator with excellent performance to improve the overall ADC performance.This thesis will design a high-speed,high-precision pipelined ADC,and focus on the comparator.This thesis first gives an overview of the basic principle of pipelined ADCs,and then introduces the key technologies of pipelined ADCs,including sample-and-hold circuit,MDAC,Sub-ADC,etc.,with a focus on the comparator and an analysis of its function,performance and implementation.Then the performance index of the ADCs designed in this thesis is determined,and each module is designed according to the index,including the design of bootstrap switch,the design of MDAC structure,the design of op-amp in MDAC and the design of Sub-ADC,etc.The comparator is designed with emphasis on the comparator.A switched-capacitor pre-amplified regenerative comparator is designed.The output common-mode voltage is stabilized by adding a common-mode feedback resistor to the preamplifier and two cross-coupling capacitors to the latch to increase the speed of the comparator.And a static comparator offset calibration technique is adopted to reduce the comparator offset voltage at the analog side.After the design is completed,the corresponding layout of the design is completed according to the circuit,and the R-C-C parameters are extracted and the post-simulation is completed.This thesis uses CMOS 40nm process to design each module of 1GSps 14bit pipeline ADC with 3bits MDAC for the first 5 stages and 4bits Flash for the last stage.The simulation software Cadance is used to simulate the circuit,and the results show that the standard deviation of the comparator's offset voltage is 6.82018m V,the triple standard deviation is less than half of the minimum resolution,the transmission delay is 11.644ps,the BER of the comparator is 6.25_?10^-15,and the total comparator power consumption is1.54m W.The area of the whole ADC is 902um×407um,and total ADC power consumption is 700m W.At a sampling rate of 1GSps and an input signal frequency of no more than 1GHz,the ADC's SFDR is greater than 74d Bc,ENOB is greater than 11.5.