9-bit 50-Ms/s SAR ADC Design With Digital Background Calibration Technique

Analog to digital convertor(ADC)is the bridge which connects the real world and the digital system.Modern portable devices drive ADC design towards high speed,high resolution and extremely low power.Compared with flash ADC and pipelined ADC,SAR ADC has the advantage of low power,moderate resolution and speed,and simple structure.It benefits from the scaled CMOS technology because most part of its circuits are digital circuits.SAR architecture has been widely used and becomes a popular region in IC design.This thesis focuses on moderate resolution and speed SAR ADC design using for portable electronic equipment.It proposes a 9-bit,50MS/s split CDAC based SAR ADC with digital background calibration.The ADC uses the tri-level charge redistribution technology to improve the speed of the switch capacitors,and to decrease the power consumption of the analog block.Using the dynamic comparator,which does not consume static power,to improve the speed of comparison.At last,it proposes a digital background calibration scheme by using redundant cycle.to remove the non-linearity caused by the bridge capacitor mismatches.The effectiveness of the proposed SAR ADC was verified by the post simulation results of a 9b 50MS/s SAR ADC in 180nm CMOS process.The power supply is 1.8 V.Post simulation results show that,after calibration the DNL and INL are improved to+0.17/-0.67 LSB and +0.65/-0.57 LSB,respectively.It achieves a SNDR of 52dB at the nyquist frequency.The total circuit consumes current of 2.7mA,in which the digital block consumes 2.2mA and the analog block consumes 500uA.