Digital Enhancement Technique For Analog Circuits In Deep Sub-micron CMOS

As the CMOS technology keeps scaling down, more and more design difficulties are raised for precise or highly linear analog/RF circuits, mostly due to the decreasing transistor intrinsic gain and the shrinking voltage headroom. In order to release such design headache and improve the circuits'performance, like linearity, bandwidth, power consumption and so on, a digital enhancement technique is adopted in recent years, which utilizes digital signal processing to boost the linearity. This approach helps to move the design difficulties from analog/RF domain into digital domain, therefore benefiting from the technology downscaling, in terms of fabrication cost and power consumption.In this thesis, the digital enhancement technique for analog circuits in deep sub-micron CMOS process is further exploited. As a background survey, the impacts of CMOS technology downscaling to digital, analog and RF circuits are described in details. Then both conceptual insight and generic design methodology of the digital enhancement technique are systematically discussed. Thereafter, two examples following the proposed design methodology are presented, demonstrating the advantages of the digital enhancement technique.The first example is an integrated CMOS RF power amplifier utilizing digital predistortion for linearization. A novel multi-level look-up table based predistortion algorithm with fast adaptation and loop delay compensation is proposed. Furthermore a WLAN transmitter prototype utilizing digital enhancement technique are developed, where besides the PA nonliearity, the digital predistortor are also dealing with other transmitter impairments, such as analog baseband nonlinearity, quadurature modulator imbalance, non-flat frequency response and etc. The experimental results illustrates that digital enhancement technique helps to boost the transmitter linearity while maintaining high power efficiency.The second example is the digital background calibration for pipelined ADC, where a new, virtual-channel based calibration algorithm is developed. This calibration scheme can compensate the pipelined ADC nonlinearity caused by capacitor mismatch, finite amplifier open loop gain, and harmonic distortion, without obvious cost and power consumption penalty. Both behavior-level simulation and preliminary circuit-level simulation results are shown, justifying the effectiveness of the proposed ADC calibration algorithm.Lastly, several practical issues related to digital enhancement technique are summarized, and the future developing trend is also investigated.