Research And Design Of High Speed And High Precision ADC Based On Pipelined Structure

Pipelined ADC is widely used in Digital signal processing system because it is the transmission link between the real world and the virtual world.With the development of information technology and CMOS technology,the requirements of circuit system for the speed and precision of ADC is getting higher and higher.Because of its high speed,precision and flexible structure,the pipeline ADC has become the mainstream system architecture in the field of high speed and high precision ADC design.Based on SMIC180nm CMOS process and 1.8/3.3V power supply voltage,a high-speed pipeline ADC with 14-bit resolution is designed in this thesis.Firstly,the influence on the overall performance of ADC that is caused by the precision selection of each stage is studied in this thesis.The lower accuracy per stage is beneficial to improve the ADC conversion rate,while the higher accuracy per stage is beneficial to improve the ADC accuracy.After a comprehensive consideration of the two schemes,the pipelined architecture is finally determined to be 3.5b×3+5b.The requirement of comparator offset is increased by the higher accuracy of each stage,so the redundant calibration technology is adopted between each stage to reduce the influence of comparator offset on ADC accuracy.At the same time,the number of comparators is also increased by the higher accuracy of each stage,so in order to reduce the number of comparators in the last stage,a two-stage FLASH ADC is designed.To realize this two-stage FLASH ADC,a two-stage pre-magnified comparator is designed for sequential coordination and improving the resolution of the comparator.Finally,the number of comparators is reduced from 31 to 13 without affecting the conversion rate and accuracy.In addition,in order to reduce power consumption and area,SHA-less sampling circuit is adopted in this thesis.However,by using this sampling method,the input signal of large swing is processed directly by the sampling switch and comparator at the first stage,it may cause the leakage of the sampling switch and the errors of the sampling results.So,In this thesis,the traditional bootstrap switch is improved to dynamically change the substrate potential so as to reduce the influence of leakage on the sampling results.At the same time,a comparator which can deal with large swing input signals is designed to adapt to this sampling mode.Finally,the calibration algorithm of gain error and capacitor mismatch error in pipeline ADC is studied in this thesis,and it has been found that in the previous calibration algorithm design,sometimes one kind of error is emphasized while the other is ignored.Therefore,a calibration algorithm combines gain error front calibration and capacitance mismatch calibration is designed in this thesis.When there are random error of 0.1%between each capacitor,the ENOB of ADC is calibrated from 8.62bit to 13.37bit,and the SFDR is calibrated from 60.8d B to 88.7d B.It verifies the effectiveness of the proposed calibration algorithm in this thesis.The simulation results shows that the 14-bit high-speed pipelined-line ADC designed in this thesis can reach 9.97bit ENOB and 67.76d B SFDR under the sampling frequency of 100MS/s and input signal frequency of nyquist,the overall power consumption is about 390m W,and the overall area of the layout is 4.56mm~2.