Research And Implement Of Calibration For A 14 Bit 1 GS/s Pipelined ADC

With the rapid development of science and technology,especially the digital signal processing and communication system,as the interface of analog signal and the digital signal,analog-to-digital converter is proposed ever-increasing demands,mainly for the design of high-speed,high-precision and low-power consumption.Pipelined ADCs have advantages over other ADCS in terms of speed,accuracy,area and power consumption.Therefore,high-speed and high-resolution pipelined ADCs are one of the current research hotspots of ADC.But as CMOS process sizes and voltages continue to drop,the design of high-performance analog circuits becomes more difficult.Therefore,improving performance through the aid of digital calibration algorithms has become one of the important research direction of pipeline ADCs.This paper first analyzes the various error sources of the pipeline ADC,and completes the behavior modeling of the pipeline ADC,which provides a platform for simulating different calibration algorithms under actual error conditions.At the same time,this paper studies the basic principle of digital calibration of pipeline ADC,and based on this,proposes a novel dither injection technology.This novel dither injection technique can effectively suppress the nonlinearity caused by insufficient amplifier gain with the inter-stage transfer function unchanged.Next,we minimize the comparator offset voltage by digitally correcting the offset voltage of the comparator inside the ADC.In addition,we use correlation-based digital background calibration and capacitance mismatch calibration to reduce the dynamic error of the MDAC,thereby improving the SFDR of the pipelined ADC.The pipelined ADC is fabricated using a 28 nm CMOS process.Due to the application of digital assist technology,the chip has a footprint of 3 mm2 and consumes 0.75 W of power,effectively reducing power consumption and area.The chip measurement result indicates that when the input signal is an 84 MHz and-2 dBFS analog signal,the INL is improved from the-5/+7.8LSB before calibration to the calibrated-2.4/+3.6LSB,the dynamic parameter SNR increased from 51 dB before calibration to 62 dB after calibration,and the SFDR increased from 61 dB before calibration to 72 dB after calibration.achieving significant results.