12bit 2GS/s Hybrid Structure ADC Circuit Design

Connecting analog worlds and digital circuits,Analog-to-digital converters(ADCs)play a vital role.Especially with CMOS processes scaling down,analog integrated circuit design encounters many difficulties.With the data processing speed of electronic system rising increasingly,the improvement of ADC performance has become an urgent problem to be solved.In recent years,many new types of high-performance and low-power ADCs have been developed.This thesis firstly analyzes some of GHz low-power ADC design techniques,such as sample-and-hold amplifier-less,time-interleaving,range-scaling,inter-stage capacitor sharing,redundant bit technique,and the analysis of Sub-ADC based on Pipelined SAR structure.To deal with the aperture error caused by the sample-and-hold amplifier-less technique,the aperture error elimination technique of combining sampling channels is used,and a custom 3-bit sub-circuit with 1-bit redundancy is proposed.The use of rangescaling technology makes the reference voltage of the subsequent circuit half of the first level.Inter-stage capacitor sharing technology reduces the load of the first stage,but also needs an additional phase to eliminate the charge memory effect.Redundant bit technology can be used to correct the aperture error of the circuit sampling networks and tolerate a certain degree of comparator offset,improving the accuracy of ADC.Time interleaving technique can double the ADC sampling rate while consuming low power.Secondly,the system structure and working principle of the 12 bit 2GS/s hybird structure ADC are analyzed.The later Pipelined SAR ADC uses 5bit SAR ADC bottom capacitor sampling and 6bit SAR ADC top capacitor sampling,split-capacitor array,optimized fully dynamic comparator,high speed SAR logic,fully customized sequential selected signal and logic control signal generation circuits,simple and highly efficient dynamic residue amplifier and its calibration circuits,and improved sampling bootstrap switches.The residue amplifier has been carefully designed and optimized,and a calibration circuit with stable gain under different process corners has been added.Based on the time interleaving technology,a three-stage hybird structure ADC circuits was built and integrated simulation was performed.Each stage of the 12-bit 2GS/s hybird structure ADC was pre-simulated under different frequencies,amplitudes,and noises of the input signals.With an input signal of 101.56 MHz,-1 dBFS,and a sampling rate of 2 GS/s,the ENOB of the overall three-stage hybird architecture is 11.34 dB,SFDR is 80.4 dBc,and SNDR is 70.0 dB.Under the post-simulation with the SAR ADC layout,the simulation results slightly decreased.Finally,the other content of this thesis is to propose two innovative fully dynamic comparator with offset self-calibration techniques,one is offset voltage storage calibration technology,whoes principle is investigated by theoretical analysis in detail,and Monte Carlo simulation method is used to vertify the comparator's offset calibration effect.And the principle of another fast convergence comparator with offset selfcalibration circuit is introduced.