Research And Design Of Multi-stage Pipelined SAR High-speed ADC

Analog-to-digital converter(ADC),as the link between analog and digital signals in integrated circuits,plays an important role in various circuit systems.With the continuous advancement of technology,integrated chips have put forward higher speed,higher precision and lower power consumption requirements for analog-to-digital converters.Pipelined ADCs have always been the first choice for high-speed and high-precision ADCs.By cascading multiple sub-ADCs,Pipelined ADCs can achieve high precision and speed,but due to the presence of residual amplifier between adjacent pipeline stages,the power consumption will be higher.In the low power application scenario of ADC,the successive approximation analog-to-digital converter(SAR ADC)is indispensable.The serial working principle makes its structure relatively simple,and has the advantages of low footprint and low power consumption.But the sampling rate and precision can not meet the high requirements.In order to combine the advantages of the above two ADCs,a pipelined successive approximation analog-to-digital converter(Pipelined SAR ADC)emerged as the times require,and has gradually become a hot topic in the current research on analog-to-digital converters.This thesis designs a Pipelined SAR ADC with 12 bits precision and 400 MSPS sampling rate.Firstly,through the analysis of power consumption,speed and redundancy range,the pipeline stages and precision of each level of the ADC are determined,and the first-stage sub-ADC is adopted.A two-stage pipeline structure with 7-bit precision and 1-level internal redundancy,and 8-bit precision for the second-stage sub-ADC,introduces2-bit inter-stage redundancy,and the final effective precision is 12 bits.In order to meet the requirement of high sampling rate of 400 MSPS,a non-binary capacitor array is used in the first-stage sub-ADC to reduce the requirement of DAC voltage establishment time,and a high-speed comparator with adaptive asynchronous logic is adopted,which greatly improves the time utilization Rate.Asynchronous sequential logic is used in sub-ADCs and between stages to reduce time waste.The residual amplifier between stages adopts a dynamic residual amplifier based on charge sampling,and compensates the gain in an analog way to reduce the gain change under PVT.In this thesis,the overall circuit construction and layout drawing of the 12-bit400MS/s Pipelined SAR ADC are completed under the 28 nm process,and the system simulation is carried out with the help of spectre and hspice tools.When the power supply voltage is 1.1V,the sampling frequency is 400 MHz,and the input signal frequency is the Nyquist frequency,the post-simulation results show that the signal-to-noise-distortion ratio(SNDR)reaches 62.09 dB,the effective number of bits(ENOB)is 10.02 bits,the Spurious-Free Dynamic range(SFDR)is 70.18 dB,and the performance index meets the design requirements.