Research And Design Of 10GSps Analog-to-digital Converter

The data converter is the hub connecting the digital signal and the analog world in signal processing,and is the key module of the mixed signal processing system.With the demand for highspeed signal processing applications such as optical carrier radio and broadband communication technology,the speed and bandwidth requirements of analog-to-digital converters(Analog-toDigital Converter,ADC)are getting higher and higher.Studying single-core ultra-high-speed and ultra-wideband ADCs is of great significance for high-speed signal processing and other related engineering fields.This article first introduces the basic principles and main measurement indicators of analogto-digital converters,compares the advantages and disadvantages of commonly used high-speed ADC architectures,studies the main difficulties of ultra-high-speed ADC design,and then selects the fully parallel ADC with the highest conversion rate as the design direction of this topic To study its system architecture and key technologies.At the system level,the idea of modularization is used to improve the topology structure of the traditional fully parallel ADC,and the bottom ADC unit module is spliced to achieve higher ADC functions,and the system design of the fully parallel ADC is optimized.At the circuit level,this article studies and designs the ADC module circuit under highspeed applications.The principle and error source of the sampling system are analyzed,and the gate voltage bootstrap switch is improved to realize a high-speed sample-and-hold circuit.For input signals within a bandwidth of 3GHz,the effective number of bits of the output signal exceeds 7bits at a sampling frequency of 10 GHz and works at 20 GHz At frequency,the effective number of output bits also reaches more than 6 bits.A two-stage pre-amplifier plus latch cascade is used to implement a high-speed dynamic latch comparator circuit.At an operating frequency of 10 GHz,a 0.5 m V voltage is input and the comparison time is only 57 ps.The high-speed digital encoding circuit first converts the thermometer code output by the comparator array into a 1 / n linear code with a high operation error tolerance rate,and at the same time eliminates the first-order bubble code error,and then converts it into a general binary code through a binary encoding network.Finally,using the improved full-parallel architecture of this article,based on the TSMC 40 nm LP CMOS process,a 4-bit low-level ADC circuit module was built,and then spliced into a 6-bit ADC to complete circuit and layout simulation.The overall circuit layout area of the ADC is1.86mm2.The post-simulation results show that at a sampling frequency of 10 GS / s and an input frequency of 3.2421875 GHz,the SNDR is 33.24 dB,the SFDR is 44.6dB,and the ENOB is 5.229 bits.