Design A High Speed, High Accuracy And Low Power ADC In 0.6um Technology

Analog-to-digital converters (ADCs) find wide application in many fields such as comminication and data collection. High speed and high resolution is a trend of the development of modern analog-to-digital converter technology. Pipelined analog to digital converter, becouse of its high speed ,high resolution, small chip area and good dynamic performance, is widely adopted.The purpose of this dissertation is designing a high speed high resolution ADC. This ADC adopts 9 stage , 1.5bit/stage pipeline architecture, with 10 bit resolution and speed no less than 20MS/s, implemented in CSMC 0.60um DPDM CMOS process. The digital correction technique is used to relax the offset requirement of the comparators. To reduce signal-dependent charge injection and substrate noise injection, the bottom-plate sampling technology is applied. A sample-and-hold amplifier (S/H Circuit) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. Furthermore, the ADC consumes 49mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.This dissertation analyse the architecture of the pipelined ADC. This dissertation presents the architecture and design process of dynamic comparator, in detail. The simulation results indicate that with 5V power supply the proposed comparator architecture can work under 400MHz clock frequence with lower than 30mv offset and 36*141 um2 layout area. The layout design of the proposed pipelined ADC has been finished and the test chip is being implemented.The simulation results indicate that the proposed comparator architecture can fully meet the requirment.