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12bit 300MS/s Sample And Hold Circuit Based On 40nm CMOS Process

Posted on:2017-01-07Degree:MasterType:Thesis
Country:ChinaCandidate:H G WuFull Text:PDF
GTID:2308330485988302Subject:Microelectronics and Solid State Electronics
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With the rapid development of computer and mobile communications, the demand for high-speed and high-precision ADC system increase quickly, ADC develop in the direction of high-speed, high-precision and low power consumption. Pipeline ADC can achieve a good compromise between high speed, high precision and low power consumption, so it is increasingly becoming the focus of the direction we study. Sample and hold circuit is typically used as an analog front-end circuit of pipeline ADC, the overall error of ADC circuit is also determined by the front-end circuit. So the study of high-speed and high-precision sample and hold circuit is important.This thesis studies the theory and circuit implementation of sample and holds circuit. It covers sample and hold theory, sample and hold structure, sample and hold error source, sample and hold settling model, high-performance sampling switch, and high speed high-gain operational amplifier. Finally, a 12 bit 300MS/s sample and hold circuit is designed based on 40 nm CMOS process.The details include:1. This thesis systematically compares the advantages and disadvantages of the different sample and hold circuit configuration. Based on 12 bit 300MS/s performance, to reduce the power consumption, the switched capacitor flip-around sample and hold circuit is selected for the design.2. This thesis analyzes error sources of the sample and hold circuit and method for reducing errors. The sampling switch is the main source of error. So high-performance sampling switch structures are analyzed. Finally, a high-speed and high-precision bootstrapped switch is designed, which is suitable for this application.3. This thesis studied sample and hold circuit settling model and the relationship between it and the operational amplifier. Based on deduced gain relationship between it and the operational amplifier. Based on deduced gain and GBW of operational amplifier, the gain-boosted operational amplifier is choosed, and mixes different withstanding voltage MOSFET to optimize the performance.4. In this paper, based on the above theoretical analysis and implementation considerations, a 12 bit 300MS/s sample-hold circuit is designed in 40 nm CMOS process. Simulation results show that the settling time is 1.37 ns, SFDR is 93.1dB, and power dissipation is 67.1mW.
Keywords/Search Tags:analog-to-digital converter, bootstrapped switch, high speed high-gain operational amplifier, high speed high-precision sample-hold circuit
PDF Full Text Request
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