Research And Design Of High-speed High-precision Pipelined Adc Cell Circuit

The development of high-speed high precision ADC has been accelerated with the quick development of the computer, multimedia, communication, microelectronic and the wide applications of the image display, high performance controller and the transport. It is not substituted that the ADC acts as the interface of the analog signal and the digital signal. The process compatibility, limitation of the power consumption and the area, and the noise are the handicap for the design of the high-speed high precision ADC. So the study aiming at the high-speed high precision ADC is becoming the focus.The key unit circuit of the 8 bit pipeline Analog to Digital Converter is researched in this paper. The Analog to Digital Converter, which hold the 250MSPS sapling rate and 700MHz bandwidth, has been taken out based on the Zarlink 0.35μm BiCMOS process. At present, the ADC chip has been applied successfully.The tasks of this thesis are shown as follows:1. The online digital trimming (OLDT) technique is researched in the design of the ADC. The OLDT hold the repeatability, flexibility, and high efficiency by adopting digital control circuit and MOS switch. The error coming from the process is eliminated by the digital trimming technique, and this trimming technique can be widely applied in the design of the analog integrate circuit.2. The high performance broadband T/H circuit is designed. The channel charge injection and the clock feed through are eliminated by adopting the full difference structure and the Bottom-Plate Sampling. The nonlinear error is eliminated by adopting the Bootstrapping switch. The broadband high gain is achieved by adopting common source common base and the common source common gate structure.3. The high performance residue amplifier is designed. The data transmission and operation is carried by the subtraction gain function of the residue amplifier. The DNL error is eliminated by optimizing the capacity and the switch. The linearity and the precision are enhanced.The 8bits ADC adopts the 5 stages 1.5bits per stage and the 3bits Flash structure, which hold a compound structure of the pipeline and the flash structure. This structure can not only improve the speed and the precision, but also decrease the power consumption and the area. The value of the DNL and the INL is the±0.3LSB and the 0.25LSB respectively by optimizing the design of the circuit.