Research On High-speed Low-power SAR A/D Converters In CMOS Process

With the explosive growth in computer processing and microelectronics technology,the speed of digital signal processing is becoming faster.As the key interfaces in mixed-signal systems,Analog digital converter?ADC?has become more and more important.There are higher requirements for the ADC performance.Due to the simple structure,low power consumption and easy integration,successive approximation register analog to digital converter?SAR ADC?is widely used in industrial control,high speed transformation and data/signal acquisition system.Based on the structure of SAR ADC,this paper focuses on analyzing and researching the key technology of the high speed low power SAR ADC,and puts forward several effective solutions to improve the circuit speed and power performance.An 8bit 500MS/s single-channel asynchronous SAR ADC,which is designed in 65nm CMOS technology,is proposed in this paper.By employing the asynchronous technique and full-custom SAR logic control unit,a better match between SAR logic control unit and sub-DAC settling time can be obtained;the split capacitor array technique and reused terminating capacitor technique are applied to decrease the sub-DAC settling time with appropriate resolution;the full-custom SAR logic control unit improves the signal transmission speed and reduces the delay of digital circuit.The simulation results show that the 8bit 500MS/s SAR ADC consumes 2.15mW with a 250MHz sinusoid input signal.The ADC achieves a SNDR of 49.89dB and a ENOB of 7.99bit,resulting in a figure of merit?FOM?of 16.9fJ/Con-step.A 10bit 250MS/s configurable single/differential input end SAR ADC in 55nm CMOS technology is presented.The SAR ADC is used in image signal acquisition and processing system.The work put forward several innovative structures of sample and hold circuit to realize the configurable single/differential input end function;the paper details the sub-DAC capacitor array based on split technique and gives consideration on both the function and performance;the study aims at the mismatch in the design of the circuit layout.The homocentric symmetric structure and square cross structure are applied to improve the devices dimensional matching and reduce the mismatch error.In the single-ended mode,The SNDR of the 10bit 250MS/s SAR ADC is 53dB with a 125MHz sinusoid input signal and the power consumption is 2.81mW,resulting in a FOM of31fJ/Con-step.Meanwhile,in the differential operation mode,the SNDR is 56.5dB and the power consumption is 3.43mW,resulting in a FOM of 25fJ/Con-step.An ultra-high-speed multistage track-and-hold circuit and voltage follower in 65nm CMOS technology are proposed,which are used as front-end circuit in ultra high-speed 16-way time-interleaved?TI?SAR ADC.The sample and hold circuit adopts the multi-stage architecture,which could eliminate the time skew between different channels in TI SAR ADC;the multi-stage architecture can make the sampling rate of 10GS/s down to the rate of sub-ADC?625MS/s?;by shunt-peaking inductance technology,the bandwidth of the first-stage track-and-hold amplifier is enhanced;clock feed-through canceller is adopted to improve the accuracy.The proposed track-and-hold circuit is simulated at a sampling rate of 10GS/s and 6bit ENOB is achieved with input frequency up to 5GHz.Several non-ideal effects in the high-speed low-distortion voltage follower are analysed,including the channel length modulation and the body effect;the non-ideal effects are eliminated by cascode transistors and quasi-floating bulk?QFB?technique.The simulation result shows that the improved circuit achieves over 60dB SFDR with a 1.2V_ppp 1GHz differential sinusoid input signal.