Research And Design Of Integration Circuit Of The High-Speed High-Precision ADC

The development of high-speed high precision ADC has been accelerated with thequick development of the computer, multimedia, communication, microelectronic andthe wide applications of the image display, high performance controller and thetransport. It is not substituted that the ADC acts as the interface of the analog signal andthe digital signal. The process compatibility, limitation of the power consumption andthe area, and the noise are the handicap for the design of the high-speed high precisionADC. So the study aiming at the high-speed high precision ADC is becoming the focus.The innovative productions concerning the design of the ADC are shown in thefollowing. The online digital trimming(OLDT) technique, the mixed analog-digitaltransition structure, the high performance residue amplifier, the high performancebroadband track and hold(T/H) circuit, and the code density and the cohere testingprinciple are brought forward in the design of the ADC. The static and dynamicparameters and can be tested easily by applying the high speed collecting card. The8bits ADC device based on the 0.35um BiCOMS process with the 250MS/s samplingrate and the 700MHz band width has been taped out and is applied successfully in thedefense engineering equipments.The innovative result of the paper is shown in the following:1. The online digital trimming(OLDT) technique is applied in the design of theADC. The OLDT hold the repeatability, flexibility, and high efficiency by adoptingdigital control circuit and MOS switch. The error coming from the process is eliminatedby the digital trimming technique, and this trimming technique can be widely applied inthe design of the analog integrate circuit.2. An 8bits ADC device with the 250MS/s sampling rate and the 700MHz bandwidth has been designed, which hold a compound structure of the pipeline and the flashstructure. This structure can not only improve the speed and the precision, but alsodecrease the power consumption and the area. The value of the DNL and the INL is the±0.3LSB and the 0.25LSB respectively by optimizing the design of the circuit.3. The high performance residue amplifier is designed. The data transmission and operation is carried by the subtraction gain function of the residue amplifier. The DNLerror is eliminated by optimizing the capacity and the switch. The linearity and theprecision are enhanced.4. The high performance broadband T/H circuit is designed. The channel chargeinjection and the clock feed through are eliminated by adopting the full differencestructure and the Bottom-Plate Sampling. The nonlinear error is eliminated by adoptingthe Bootstrapping switch. The broadband high gain is achieved by adopting commonsource common base and the common source common gate structure.5. The value of the SNR, the ENOB, and the THD is the 41.31dB; 6.57Bits; 51.77dB respectively when sampling with the 250MHz to the 125MHz input signal. Theprocess is the XFAB and the Jazz semiconductor 0.35μm BiCMOS.6. The static parameter and the dynamic parameter are tested by the code densityand the cohere testing principle, and the high speed collecting card is applied in thetesting...