Research On Key Techniques Of Pipelined Successive Approximation Analog-to-Digital Conversion

With the development of semiconductor technology,most of the electronic systems have higher and higher requirements for the analog-to-digital converters(ADCs).Traditional ADCs are already difficult to handle.In order to adapt to the increasing demands,research on high performance hybrid ADCs is imperative.As a typical hybrid ADC,the pipelined successive approximation ADC(Pipelined SAR ADC or Pi-SAR ADC)combines the advantages of Pipeline ADC and SAR ADC.It is a hot research direction of high performance ADC in recent years.This dissertation takes the key techniques of Pi-SAR ADC as the research topic.Based on the theory of SAR ADC and Pipeline ADC and the existing Pi-SAR ADC techniques,some key techniques have been deeply studied,such as the architecture optimization technique of Pi-SAR ADC,high linearity sample-and-hold circuit technique,and low power residual-amplification technique,mismatch calibration technique and time interleaving technique based on Pi-SAR ADC.Finally,most of the techniques are physically verified in a 16-bit 125MSPS two-channel time-interleaved Pi-SAR ADC.The Spurious-Free Dynamic Range(SFDR)of 82.73 dBc and the Signal-to-Noise and Distortion Ratio(SNDR)of 72.44dBc are realized with a power consumption of about 8 mW at 1.2 V supply voltage.The Effective Number of Bits(ENOB)is 11.74 bits and the Figure-of-Merit(FOM)is 18.9fJ/conv.-step.The main work of this dissertation is as follows:(1)A dynamic-capacitor-mismatch calibration technique and a gain mismatch calibration technique based on second derivative of transfer curve are proposed.The former uses the gate parasitic capacitance of MOS device to correct the dynamic-capacitor-mismatch,which is caused by the nonlinear parasitic capacitance of the input pair of comparator.By using the technique,the linearity and signal-to-noise ratio(SNR)is improved at the cost of the two MOS devices.The latter carries out inter-stage gain mismatch calibration based on the second derivative of the ADC output characteristic curve near the turning point between the residual transfer curve.It requires only 1.5×10~4 cycles for gain calibration in a Split-Pipeline ADC.(2)A high-speed and high-linearity sample-and-hold circuit technique based on parasitic capacitance compensation is proposed.It compensates the nonlinear parasitic capacitance and the input signal feedthrough by paralleling a MOS transistor of the same size but opposite type as the sampling switch.By using the upper-plate gate-voltage-bootstrap?-type CMOS common-mode switches with substrate voltage switching technique,the nonlinear resistance of the common-mode switches is reduced.Compared to conventional gate-voltage bootstrap hold-and-hold circuits,the linearity is improved by 11 dBc.In addition,in order to improve the speed of SAR ADC,a high-speed quasi-static latch circuit based on data trigger logic is proposed.With this technique,the speed of the SAR Cell circuit increases by 60%while the power consumption reduces by about 50%.(3)Two kinds of quantization techniques based on comparator delay information are proposed:2b/cycle high-speed quantization technique combining voltage domain and time domain and delay information-assisted local oversampling technique.Both techniques are based on the theoretical basis that the comparator delay in the SAR ADC monotonically decreases as the input amplitude increases linearly.Compared with the traditional 2b/cycle quantization the former has fewer comparators and the reference delay is generated by the controllable delay chain.Compared to the traditional 1b/cycle quantization,the same speed can be achieved at a lower voltage.In both cases,it is beneficial to reduce power consumption.Compared with the traditional oversampling technique,the latter does not require extra oversampling periods,and can achieve the purpose of reducing noise and improving SNR while ensuring the same sampling rate.(4)A low-power and high-stability dynamic open-loop residual amplification technique based on charge sampling is proposed.Due to charge sampling,it achieves low noise.By using full asynchronous timing,it simplifies the clock generation circuit and improves the speed and stability,simultaneously reduces the circuit noise.The new sampling timing avoids the charge injection and clock feedthrough of the current source switches.Finally,the proposed PVT(Process,Voltage and Tempreature)stabilization technique of gain suppresses the gain-variation of an integrator-like open-loop dynamic Residual Amplifier(RA).With this technique,the gain variation is reduced by 81.13%,94.51%and 98.32%,respectively.