New Structure Research Of High Speed And Low Power Of SAR ADC

As the interface of analog and digital domain,the performance of Analog-to-Digital Converter(ADC)restricts the performance of the whole system.Without high performance operational amplifier,Successive Approximation Register(SAR)ADC provides lower power consumption and smaller die area compared to other ADC structures.As the improvements of integrate circuit process,the power voltage and length of MOSFET is reducing and the frequency of MOSFET is increasing,the sampling rate of SAR ADCs increases obviously.Thereby,SAR ADCs could satisfy the requirement of many electronic systems,such as telecommunication,radar,instruments,measurement and control.Thus,SAR ADCs become one of the major research domain in analog to digital conversion.Nowadays,in 55 nm or 65 nm CMOS process,the Figure of Merit(FoM)for 8b 300MS/s or 10 b 150MS/s SAR ADC is mostly around 30fJ/conv.Firstly,this dissertation introduces the mainly architectures,operational principles,applications and characteristics of ADCs,the advatages of SAR ADC in advanced integrate circuit process is indicated.The key techniques of speed,precision,power consumption,noise and mismatches in the design of SAR ADC are also provided.Farther,the elementary structures and operational principles of SAR ADCs are introduced.The working pattern and difficulties of key blocks are also analyzed.In addition,aiming at the research of key blocks in high speed and low power SAR ADC,this paper proposes high speed and high linearity sampling switch,high speed low power comparator and high speed SAR logic structures.In 55 nm and 65 nm CMOS process,the difficulties of sampling switch linearity and SAR logic speed improvement,meta-stability and noise immunity of high speed low power comparator for SAR ADC are resolved.After tape out and test,the proposed innovative structures provide <30fJ/conv FoM for SAR ADCs.Based on the analysis,the specific research contributions include:(1)A linearity-improved sampling switch structure with parasitic capacitance compensation is proposed.For sampling switch,the voltage coefficient of parasitic capacitance is reduced.In the condition of signle input Vp-p is 1V,the Spurious Free Dynamic Range(SFDR)of sampling switch is improved about 5.5dB compared to previous structures.(2)A metastability immunity structure is provided to suppress the uncertain decision behavior of high speed and low power dynamic comparator.Compared with existing techniques,the comparator provides more than 1.3 times faster with less 85% power consumption.Because of minimal delay in the signal path,the compare delay is reduced 26%.(3)A bypass SAR logic structure that parallels comparator and SAR logic operations is exhibited to reduce the delay of SAR feedback loop.The valid outputs of comparator are catched by SAR logic step by step.The conversion speed of SAR ADC is increased about 30% compared to conventional structure.(4)A substrate floating structure for linearity improvement of sampling switch is proposed.For sampling switch,the total parasitic capacitance and voltage coefficient of parasitic capacitance are both reduced compared to conventional structures.As the signle input Vp-p changes from 0.6V to 1.2V,the deterioration of SFDR is restrained about 4.5dB.(5)A substrate voltage boosting structure is proposed to depress the noise of comparator at high conversion rate.The transconductances of input MOSFETs are improved to dpress the input referred noise.In addition,the on-resistances of of input MOSFETs are rudeced to increase the compare speed of comparator.Compared with existing techniques,the comparator provides 17% faster with 31.5% noise reduction.(6)An asynchronous sampling structure is proposed to maximize the sampling time.A new sampling period begins immediately as the end of last conversion,thus,the sampling time is maximize compared to conventional mode and the precision of sampling is increased.