Design Of A 12-bit SAR ADC With Capacitor Mismatch Calibration Based On Comparator Metastability

With the development of science and technology,signal processing is also becoming more and more digital,but the real world signal is continuous analog signal.As an important bridge between digital signal and analog signal,the analog-to-digital converter(ADC)is a very important circuit module.The success approximation register analog-to-digital converter(SAR ADC)has received extensive attention because of its low power consumption and medium resolution.Capacitor mismatch is one of the key factors affecting the performance of SAR ADC.For SAR ADCs with more than 10 bits,the presence of capacitance mismatch makes it difficult to further improve the resolution of the ADC.At the same time,in order to further increase the speed,the size of the capacitor array also needs to be reduced,which makes the problem of capacitor mismatch more significant.Based on the CMOS 40 nm process,this paper designs a 12-bit SAR ADC based on the metastability of the comparator for capacitance mismatch calibration and completes the layout design for post-simulation.The metastability of the comparator describes a state where the speed of the comparator is so slow that it cannot give a result for a long time,and the input voltage of the comparator in this state is very close.The calibration algorithm uses this feature as a sign and gives the ideal codes when there is no capacitor mismatch.By comparing the actual output codes of the ADC with the ideal codes,the capacitor mismatch is obtained and the calibration can be carried on.In order to avoid the long-term no comparison result brought by metastability,the pseudo-random code will replace the output of the comparator.In addition,in order to avoid false judgment caused by pseudo-random code injection,redundant bits are added to the capacitor array of the ADC.The redundant bit plays a role of fault tolerance,and can correct the false judgment caused by the pseudo-random code injection.In addition,in this paper,the redundant bit only participates in the quantization process of the digital-to-analog converter and not the sampling process,thereby generating redundant codeword space for accommodating offset voltage.The overall implementation and post-simulation of the ADC is given and the effect of capacitance mismatch calibration is verified.After the capacitor mismatch calibration,the SNDR and ENOB of the ADC have increased by 9.15 dB and 1.52-bit,respectively,and the ENOB has reached 11.71-bit compared with 10.19-bit before calibration.In the post-simulation,under the tt corner,the ADC reaches 11.77-bit at a sampling rate of 130 MHz and its FoM is 38.45fJ/conversion-step.Even if noise is added,the ADC can reach 11.50-bit in the post-simulation.By changing the frequency of the input signal,it can be verified that even when the input signal is close to the Nyquist frequency,the performance of the ADC still has a good performance,and its ENOB reaches 11.73-bit.