Research And Design Of Digital Calibration Technique For Pipelined Successive Approximation Analog-to-Digital Conversion

With the development of the high bandwidth and low latency wireless communication network,to achieve wireless communication rates up to Gbps,as well as long-term battery life on mobile intelligent terminal,Analog-to-Digital Converter(ADC),which works as an important part in wireless communication systems,is required to meet many performance metrics including high sampling rate,high precision,and low power consumption.However,traditional ADCs are difficult to satisfy such requirements.Since the hybrid ADCs contain many advantages of other kinds of ADCs,the research of the hybrid ADCs has become a hot topic in recent years.The pipelined successive approximation ADC(Pipelined SAR ADC),which combines the advantages of SAR ADC and Pipeline ADC,is able to meet the requirements for high speed,high precision,and low power consumption.However,some non-ideal factors of two ADCs are also retained in the Pipelined SAR ADC,which seriously limits its performance.Therefore,thesis aims to study the mismatch calibration of Pipelined SAR ADC.In this thesis,firstly,the capacitor mismatch,comparator offset,gain error and nonlinearity of residual amplifier in the Pipelined SAR ADC are modeled and analyzed.Analyzing and reviewing some state-of-the-art calibration schemes of these non-ideal factors.To correct both the capacitor mismatch and the gain error of residual amplifier,a digital foreground calibration technique for the Pipelined SAR ADC is proposed in this thesis.The technique utilizes the equivalence relationship of the low and high capacitors to quantify the digital weight of each capacitor,and correct the gain error of residual amplifier according to the equivalence relationship between the first stage and the second stage.Based on the 40 nm CMOS process,a 14-bit 62.5MSPS Pipelined SAR ADC was built.The result of the mixed-signal simulation showed that under mismatch,the spurious-free dynamic range(SFDR)and the signal-to-noise plus distortion ratio were improved from 46.04 dBc and 40.46 dBc to 87.30 dBc and 76.78 dBc respectively.And the effective number of bits(ENOB)was improved from 6.43 bits to 12.46 bits.To support this calibration technique,the hardware overhead in analogy circuit only requires some multiplexors and simple enable signals.And a digital calibration logic circuit optimized in area,speed,and power consumption was proposed.The circuit realizes the reuse of resources by fusing the computational logic of the calibration mode and the normal data conversion mode.Besides,it reduces critical path delay by using the addition binary tree and optimizes power consumption by adopting a variety of gating techniques and the multiple threshold-voltage technique.Under 1.1 V supply voltage and 125 MHz clock frequency,the power consumption of the digital circuit is only 0.154 mW.The digital circuit only contains 6162 gates.The feasibility of the calibration technique is fully verified in speed,area,power consumption,and calibration effect.