The Study Ofcongestion Problem Of The Crossbar Structure And The Clock Gate Timing Issue Of The Multi-point Clock Tree Structurein The Physical Design In The 14nm FinFET Process

With the decrease of the characteristic size of the semiconductor technology,the device has a short channel effect.This effect makes the leakage current increase at the sub-thresholdvoltage,and the threshold voltage of the device also decreases,resulting in the increase of chip power consumption and performance degradation.In order to improve the performance of the chip and reduce the power consumption,TSMC,SAMSUNG,GlobalFoundries have developed 16/14 nm and 7nm processes.Advanced technology gives designers greater flexibility in design,allowing them to design more complex and better-performing chips.But the advanced technology also brings great challenge to the timing closure and placement&routing of the physical design.In this thesis,we mainly study the congestion problem of the crossbar structure and the clock gating timing issue of the multi-point clock tree structurein the physical design in the 14 nm FinFET process.This thesis proposes an effective solution to the problem of the time closure and placement&routing of the physical design in the 14 nm process,especially the congestion problem of the crossbar and timing issue of the clock gate in the anmulti-point clock tree structure.In this thesis,the effectiveness of the proposed scheme is verified by a physical realization of a several millions gates module in a large SOC(system on chip).For the congestion problem of the crossbar structure,it is solved by the method of structured placement to relocation the crossbar structure,improving the timing problem caused by congestion and the violation of Design Rule.After the structured placement,simulation results show that the Total Negative Slack(TNS)of crossbar structure down from-29 ns-1.7 ns and the Worst Negative Slack(WNS)reduced from-53 ps to-38 psunder the typical mode,The number of Design Ruleviolation number reduced from 7094 to 352,Total wire length of crossbar structure module decreased from 772076 microns to 442066 microns.For the clock gate timing violation of the multi-point clock tree structure,this thesis is through the optimal placement of control logic registers,solvingthe timing violation caused by unreasonable position of the clock gate.After the optimization of the clock gate,the total TNS of the clock gate decreased from-5.6ns to-4.8nsand the WNS decreased from-135 ps to-45 psunder the typical mode.The experimental results verify the effectiveness of the proposed scheme.