| With the extensive application of memory technology, DDR PHY interface appeared. It regulated the interface of storage controller logic and cut costs as well. Owning to the high clock frequency of DDR, clock tree suffered more uncertainty from advanced technology. As a result, it’s necessary to design a DDR PHY meet both timing and power requirements. Clock tree design in digital back-end includes clock tree synthesis and clock tree optimization, the former makes the clock tree meet the design rule constraints, the latter optimize timing and power of clock tree.The method discussed in the paper was mainly for the lower design of DDR PHY. Most traditional clock tree optimization program was against clock tree structure and clock registers. The formal program has limited optimization and the latter program was difficult to realize. The method raised in the paper optimize the topology structure of clock tree. Besides, Prim algorithm and buffer allocation algorithm was raised to fulfill the clustering algorithm. Since from the beginning to the end, the location of registers was fixed. The clustering algorithm can be easily integrated into any CTS flow.The method in this paper will change the location of register so that the integrity of the netlist can be perfect. The algorithm was written by Tel language so that it can be integrated into any clock tree synthesis flow. The performance of clock tree achieved expected target in IC Compiler and the power target was meet in Voltus. |
