Multiple-Node-Upset-Tolerant Latch Designs Based On Re-Convergence And Filters

With the rapid development of semiconductor technologies,nano-scale integrated circuits are more and more vulnerable to soft errors.In CMOS technology,soft errors are mainly caused by the collision of neutrons,protons,electrons,and so on.Soft errors include single-node upset(SNU),double-node upset(DNU),triple-node upset(TNU),single-event-transient(SET),etc.It is worth noting that with the reduction of transistor sizes,it is no longer negligible for multiple node upsets to be caused by high-energy particles.At the same time,the existing circuits have poor tolerance against multiple-node upsets(MNUs),which makes the design of MNU-tolerant circuit structures become more and more important.In addition,due to the impact of high energy particles,the output of logic gate is prone to a transient voltage change,i.e.,an SET pulse.If an SET pulse propagates through logic gates to the downstream storage cell,it may be captured by the cell and cause an invalid stored value.Therefore,in order to build high reliability circuits and systems in safety critical applications,we should design circuits that can not only tolerate SNUs/DNUs/TNUs,but also can filter SETs.In this dissertation,the existing latches are evaluated and new radiation hardened latch designs are proposed.(1)A TNU self-Recoverable Latch design(TNURL)which can self-recover from any possible TNU is proposed.The latch is mainly constructed from seven soft-error-interceptive modules(SIMs).Any SIM consists of two 3-input C-elements(CEs)and one 2-input CE.Simulation results show that the latch uses redundant silicon area to realize TNU-self-recoverability.In addition,compared with the advanced TNU-tolerant latch(TNUTL),the proposed latch saves 95.45% transmission delay and 86.97% delay-power-area product.(2)A low cost,high-impedance-state(HIS)-Insensitive,TNU-Tolerant and SET-Filtering Latch design(HITTSFL)is proposed.The latch consists of an output-level SET-filtering Schmitt-trigger and three inverters,and three parallel dual-interlocked-storage-cells in the input stage.The latch achieves HIS-insensitivity by not using CEs.Simulation results show that the HITTSFL latch achieves TNU-tolerance and SET-filterability.In addition,due to the use of clock-gating and a few transistors,compared with the advanced TNUTL latch,the latch can reduce 76.65% delay,6.16% power and 28.55% area,respectively.