Design And Research Of Hardened Latch With Multi Node Upset Tolerance In Nanoscale

Single event upset(SEU)will make the logic value of latch,flip-flop and other circuits change transiently,which will affect the reliability of the chip.And with the development of Moore's law,single event upset is becoming more and more serious.Firstly,the decrease of characteristic size leads to the decrease of node capacitance and working voltage,which leads to the decrease of critical charge.The critical charge is an important indicator to reflect the difficulty of logic value upset of circuit node.The less the critical charge is,the more prone the chip is to single event upset.Secondly,the reduction of feature size makes the distance between nodes smaller,which will make a single particle affect multiple nodes at the same time and make the existing hardened structure invalid.The double node upset and triple node upset in single event multi-point upset are the focus of anti-radiation research,but it can be predicted that with the further reduction of the size,there will be more complex cases.Therefore,it is very necessary to design a structure with high reliability and suitable for smaller size according to different processes.The main work and innovation of this dissertation are as followsFirstly,the radiation effects encountered in aerospace industry are introduced,and the influence of process reduction on single event effect is analyzed emphatically.It is pointed out that single event multiple node upset has become the focus of anti-radiation research.In the second chapter,the environment,mechanism,classification and laboratory simulation methods of single event effect are introduced in detail.Then the existing hardened methods are introduced and their advantages and disadvantages are analyzed.Finally,the dissertation introduces the radiation hardened by design latch.This dissertation firstly proposes a latch scheme which can recover the triple nodes upset at internal nodes at the same time.The latch mainly uses the blocking function of dual input inverters to form a four row and six column array structure with 24 dual input inverters,in order to construct a fault-tolerant mechanism of multi-level filtering.When any three internal state nodes of the circuit are upset,the error nodes are automatically restored to the correct value through multi-layer filtering.Through HSPICE simulation software,the power consumption,delay,PDP,PVT,leakage current,aging,hardened ability and other aspects of the simulation are compared.The results show that compared with the similar hardened structure in recent years,the performance of the structure is greatly optimized.In order to solve this problem,based on the original structure,a design framework of hardened latch which can tolerate n-node upset is proposed,which can be expanded or contracted to adapt to various radiation dose and process environments.This dissertation also proposes a robust latch design framework that can tolerate n-node upset,which can be expanded or contracted to adapt to various radiation dose and process environments.Single event double node upset and single event quadruple node upset are also important aspects to be considered under the influence of charge sharing.To solve these two problems,this dissertation also makes simulation analysis on the corresponding structure under the framework,verifies its hardened performance,and compares with the existing hardened latch with the same function.When SEU occurs in the dual input inverter of the structure itself,transient current may occur.In order to improve this situation,this dissertation also proposes two more robust alternative circuits without changing the basic framework and hardened function.Finally,a hardened method for single event transient is discussed.