Research On Hardening-by-design Of Latches Protected Against Multiple-node-upsets

The reduction of transistor sizes and the drop of supply voltages make the node capacitance and the charge stored in a circuit smaller.Hence,even a smaller amount of erroneous charge can change the logic state of the node.Due to the charge sharing mechanism,a striking-particle can cause a multiple node upset,such as double node upset(DNU)and triple node upset(TNU).It is reported that multiple node upset can significantly impact circuit reliability.Under the advanced CMOS process,the traditional single node upset(SNU)tolerant latches are difficult to meet the high reliability requirements of circuits,and the multiple node upset hardening design has become an important issue that circuit designers need to consider.This thesis sufficiently analyzes many existing hardened latches,and then proposes novel radiation hardened latches protected against multiple node upsets.The main research work of this thesis is as follows:(1)A DNU completely tolerant(DNUCT)latch is proposed.The latch is mainly composed of four interlocking clock-controlled single node upset self-recovery elements and a clock-based C element.Due to the existence of sufficient feedback loops,the latch can achieve complete DNU toleration.Simulation results demonstrate the robustness of the proposed DNUCT latche.Moreover,compared with the typical TNUHL latch,the proposed DNUCT latch can improve 60% DNU self-recovery ability.(2)A TNU completely-tolerant(TNUCT)latch is proposed.By inserting a redundant level of C-elements at the output stage into the DNUCT latch,the proposed TNUCT latch can intercept node-upset errors accumulated in the upstream DICEs,so it can completely tolerate any possible TNU.Simulation results demonstrate the robustness of the proposed TNUCT latch.The proposed DNUCT and TNUCT latches are also cost-effective due to the use of high-speed transmission paths,clock gating,and fewer transistors.Compared with the typical TNUHL latch,the proposed TNUCT latch reduces the delay-power-area product by approximately 98%.