Radiation Hardened By Design Latch For Nanoscale CMOS Technology

As an IC entered the era of nanotechnology, reliability issue has become one of the most seriously concerned problems for circuit designers. With the development of semiconductor technology, the feature size of transistors continues to shrinking, together with the downgrading of supply voltage results in the decreasing of circuit node capacitance subsequently. Hence, the amount of charge stored in a node is also reduced, which makes the circuit highly sensitive to Single Event Effects (SEEs) caused by alpha particles or cosmic ray neutrons originated from packaging materials and galactic rays. With the continual improvement of the chip’s integration level, SEEs induced by radiation have become one of the most important factors that affect the reliability of integrated circuits (ICs).According to the states mentioned above, the radiation hardened methods against Single Event Effects (SEEs) has been deeply studied in this thesis, the main work is as follows:Firstly, the related knowledge of radiation environment and the classification of radiation effects are introduced, as well as the current studies on the radiation protection of ICs have been discussed. Furthermore, one of the three radiation effects, SEEs is analyzed, as well as its mechanism, classification and fault model are also thoroughly introduced. In circuit level, the principle of integrated circuit soft error caused by Single Event Transient (SET) and Single Event Upset (SEU) are also analyzed in detail.Secondly, the traditional static latch is a sensitive storage element, which is easily affected by SEU, result in soft errors occurs in ICs. To solve the problem, some hardened latch schemes proposed by domestic and overseas scholars are summarized. What’s more, the comparison of each method is also studied, and their advantages and disadvantages are also analyzed. In order to overcome the defect of existing hardened schemes, in this thesis, an SEU hardened latch based on clock-gating technology has been presented. Simulation on 45nm CMOS technology shows that the proposed hardened latch not only has a competitive advantage in performance overhead, but also can be recovered rapidly if SEU occurs on its internal node or output node.Finally, with the continuous technology scaling of ICs and the reduction of supply voltage, the contribution of SETs from combinational logics to the overall soft error rate of circuits has become more significant. Therefore, in order to ensure the reliability of ICs, an SET/SEU hardened latch based on pulse filtering and time-domain sampling technologies is proposed. The SPICE simulation on 45nm CMOS technology shows that, the proposed latch can filter SET pulses from combinational logic efficiently when working in transparent mode. Moreover, when the proposed latch is working in latching mode, if any internal node or output node of the latch is affected by energetic particle strikes, they can be recovered rapidly. Compared with the other previous SET/SEU hardened schemes, the proposed latch not only performs a higher robustness, and is also less sensitive to temperature and process variations.