Soft-Error On-Line Self-Recoverable Fault-Tolerant Designs For Latches

In nano-scale CMOS technologies,aggressive shrinking of transistor feature sizes and operation voltage in integrated circuits and systems,and thus the amount of charge required to change the logic state of a node caused by the influence of the single event effect is also reduced.Therefore,integrated circuits and systems are more subject to soft errors,and the reliability of integrated circuits and systems is particularly severe.The state of a single node can be changed due to a striking-particle,causing a soft error,which is commonly known as a single node upset(SNU).However,with the charge sharing mechanism,a striking-particle can also cause a single-event charge to simultaneously affect multiple nodes,thus causing a multiple node upset(MNU).According to relevant research data,circuits are becoming more prone to MNUs,that mainly include double-node upsets(DNUs)and triple-node upsets(TNUs).Since MNUs can increase the soft error rate of storage modules and cannot be completely mitigated by the methods targeting only SNUs,the threat of MNUs to electronic circuits and systems is becoming increasingly serious.For designers and manufacturers of highly reliable circuits and systems,MNUs have become a serious concern in advanced CMOS technologies.This dissertation first analyzes the existing design schemes of hardened latches,and then proposes a DNU self-recoverable and single-event transient(SET)pulse filterable latch design;Subsequently,a TNU self-recoverable latch is proposed.The main work of the dissertation is as follows:(1)First,this dissertation proposes a DNU self-recoverable and single-event transient(SET)pulse filterable latch(DURTPF)design for low power applications in 22 nm CMOS technology.The latch mainly consists of eight mutually feeding back C-elements and a Schmitt trigger.Simulation results demonstrate both the DNU self-recoverability and SET pulse filterability for the latch at the cost of redundant silicon area.Using the clock-gating technology,the latch saves about 55.36% power dissipation on average,compared with the up-to-date DNU self-recoverable latch designs which are not SET-pulse filterable at all.(2)Based on the information assurance through redundant design,this dissertation proposes a novel low-cost and TNU on-line self-recoverable latch(LCTNURL)design which is robustly protected against harsh radiation effects.The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements(CEs)that form a circularly linked schematic.The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs,making the latch completely self-recoverable from any possible TNU,i.e.,the latch is completely TNU-resilient.Simulation results demonstrate the complete TNU-resiliency of LCTNURL.Moreover,due to the use of fewer transistors and a high-speed path,the proposed latch reduces the delay-power-area product by approximately 36.72%compared with the up-to-date TNU self-recoverable latch(TNURL).