Design Of Low Power Fractional N Phase Locked Loop Frequency Synthesizer

A low power Sub-GHz Fractional N Phase Locked Loop(PLL)FrequencySynthesizer with Automatic Frequency Control(AFC)is designed in this paper.It contains LO distribution circuit which is used to provide quadrature signal for transmitter.Firstly,PLL system architecture is introduced and then,linear model is established to analysis the stability and transfer function of PLL.Basing on these,the noise model is also established.Secondly,a wide tuning range LC VCO is designed,which achieves 32 tuning curves through variable capacitors and capacitor arrays.And an Automatic Amplitude Control(AAC)module is designed to compensate for the difference in resonant impedance caused by changes in operating frequency and achieve adjustable gain.In addition,based on the noise model and swing-current characteristics of the LC VCO,an optimized design method with the objection of low power consumption and low phase noise is proposed.Thirdly,a local oscillator(LO)distribution circuit is designed in the phase-locked loop frequency synthesizer.This module is located behind the oscillator and provides quadrature signals for the transceiver system.It consists of a high-speed divider circuit and a high-speed buffer circuit.For current-mode logic structure and CMOS structure,the power consumption and performance of the two structures are compared and analyzed.Based on the current technology,the selection method of two structures and the optimization method of low power consumption and small area design at a given operating frequency are proposed.Fourthly,in response to the design requirements of low-power phase-locked loops,a low-power charge pump is designed and optimized for its non-ideal characteristics.A third-order Delta Sigma modulator is used to implement a fractional frequency divider and a multi-mode frequency divider is designed which is compatible with the fractional frequency divider.Aiming at the design requirements of the wideband phase-locked loop,an automatic frequency control circuit is designed to realize the automatic locking of the phase-locked loop.This paper proposes a loop filter design and optimization method based on the stability analysis of the phase-locked loop system and the noise transmission characteristics.The system noise characteristics are modeled,and the system noise characteristics are obtained by simulation analysis.The module noise is optimized and analyzed based on the system noise characteristics.This article introduces the complete design optimization process from architecture selection,parameter design to performance optimization,and obtains the test results.The phase-locked loop frequency synthesizer designed in this article is implemented in GSMC 0.13?m CMOS process and has been verified by tape-out.The final measurement result shows that under the 1.2V supply voltage,the total power consumption of the phase-locked loop frequency synthesizer including the LO distribution circuit is 3.5m W.When the phase-locked loop system is locked at 1.26GHz,the phase noise is-115d Bc/Hz at 1MHz frequency offset.The total chip area of the PLL frequency synthesizer is 0.33mm~2.