Research And Design The Digital Circuits In The Fractional-N Frequency Synthesizer

Rapid development of communication technology has put forward higher requirements for the performance of the wireless transceiver.The lock time,phase noise,frequency resolution,tuning range of the frequency synthesizer which offers local oscillating signal for transmitter and receiver affect the performance of wireless communication system directly.This paper mainly focuses on research and design of the key digital circuit in frequency synthesizer.The specific work is as follows:1)This paper analyzes the existing modulators utilizing MATLAB and CppSim,and points out the shortcomings of these modulators.To overcome these shortcomings,a novel structure of MASH 1-1-1 modulator with a prime quantization interval of P and an additional feedforward connection is proposed.The proposed modulator has a sequence length of P3,and eliminates the spurs in the power spectrum density of quantization noise.The CppSim is used to simulate the phase noise of the frequency synthesizer with different modulators.The simulation results show that by using the new modulator,the fractional spurs can be effectively eliminated,and the phase noise performance of the frequency synthesizer is improved.2)In order to solve the residual fractional error which could lead to poor performance of phase noise and even may result in the disability to lock the PLL,this paper adopts the method of counting the output signal of VCO(Voltage Controlled Oscillator),rather than the divided signal,for a period of 64 clock cycles of reference clock,introduces the rounding method,and finally the residual fractional error is reduced to 2-7 ·fref.Furthermore,for the purpose of overcoming the problem of long time consumed by the linear search algorithm,the dichotomy algorithm is employed to search the optimal tuning curve and reduce the coarse tuning time.Finite state machine is used to design and simulate the automatic frequency calibration.3)A communication protocol based on four lines SPI is customized,increasing the reliability of reading and writing operation to the chip.Sigma-Delta modulator,automatic frequency calibration and SPI interface circuits are designed and simulated using Verilog HDL language.The layout is designed using TSMC 0.18?m 1P5M process,and the area is 0.216mm2.Finally,a set of test system was designed,and the registers in the chip can be directly controlled by PC software.The test results show that the digital circuit designed in this paper work correctly,and achieved the desired performance.The power dissipation is 3.17mW and 7.87mW with 40 MHz and 100 MHz reference frequency respectively.