Research And Implementation Of The Key Technology Of CMOS Multi-mode Multi-frequency Fractional Frequency Synthesizer

The rapid development of 5G mobile communication and the rapid rise of data traffic inevitably require the future mobile communication ICs to cover most 2/3/4/5G mobile communication frequency bands and corresponding communication standards.The continuous advancement and development of CMOS technology has made CMOS technology be one of the preferred processes for multi-mode multi-frequency fully integrated RF front-end circuit implementation.Therefore,it is of great practical significance to research the design of frequency synthesizer under CMOS technology.Based on the current 5G mobile communication application scenario and the 65 nm LP CMOS process,the multi-mode multi-frequency fractional PLL frequency synthesizer that can cover most 2/3/4/5G mobile communication sub-6GHz frequency bands is studied and designed,and the corresponding technical improvement schemes for its key circuit modules are proposed.The main research contents and innovation points of the thesis are as follows:Starting from the overall structure of the PLL frequency synthesizer,the basic principle of the phase-locked loop frequency synthesizer is explained.The common performance indexes of the frequency synthesizer design are introduced,and the definition of phase noise and spurs are introduced in the spectrum purity index.Next,based on the continuous-time linearized phase analysis model,the noise transfer function of each module of the PLL frequency synthesizer is analyzed,and then the other characteristics such as stability and dynamic response of the loop are analyzed.To extend the output sequence length of the delta sigma modulator and reduce the quantization noise power spectral density effectively,the influence of modulator quantization noise on the phase noise of the fractional PLL frequency synthesizer is analyzed in detail,and then,based on the deterministic method,the single-loop negative feedback MASH DDSM structure using the negative feedback technique to form the prime modulus is proposed.The theoretical analysis and the FPGA verification show that,the structure has the largest output sequence length recorded in the literature,and it can reduce the quantization noise power spectra density of the modulator effectively.Then,based on the stochastic method,the method of using the extra dither signal to extend the output sequence length of the SP-MASH DDSM is proposed.The theoretical analysis and FPGA verification show that,the proposed method can reduce the quantization noise power spectral density of the SP-MASH DDSM effectively in the condition of semi-quantization step input.To cover most 2/3/4/5G mobile communication sub-6GHz frequency bands and reduce the power consumption,a 6-bit control word wideband VCO chip with current reuse and inductorswitch technology is designed and implemented.The measurement results show that,the VCO output frequency can be tuned from 3.991 to 9.713 GHz continuously,and the phase noise in the whole frequency tuning range is-93.09?-111.97 d Bc/Hz.With 1.2V supply voltage,the current consumption of the VCO core is varied from 3.7 to 5.1m A and the FOMT value is in the range of-191?-197 d Bc/Hz.To reduce the influence of the quantization noise of the delta sigma modulator on the phase noise of the fractional frequency synthesizer further,a 0.5-step programmable frequency divider chain using synchronous divide-by-4 phase-switching technology is designed.The postsimulation shows that,when the input frequency ranges from 5 to 12 GHz,the frequency division ratio of the divider chain covers 60.5?252,and the current consumption at 1.2V supply voltage is 9.022?10.367 m A(including power consumption of the test buffers).Moreover,for the fast lock and bandwidth offset problems in the wideband PLL frequency synthesizer loop,an automatic frequency calibration circuit using frequency comparison method and a loop bandwidth calibration unit using a programmable charge pump to adjust the charge pump current dynamically are analyzed and designed.Theoretical analysis and simulations show that,the total calibration time of the automatic frequency calibration circuit and the loop bandwidth calibration unit is 13.02 us.Finally,based on the above circuits,the layout design of the entire multi-mode multifrequency fractional frequency synthesizer is completed and delivered to tapeout.The entire chip area is about 0.94 mm × 1.06mm(including the pads).