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Design And Research Of Frequency Self - Calibration Fractional Frequency Frequency Synthesizer For Short Distance Devices

Posted on:2014-01-13Degree:MasterType:Thesis
Country:ChinaCandidate:J W ZhangFull Text:PDF
GTID:2208330434970765Subject:Integrated circuit engineering
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Short range wireless communication technique has been widely used because of having an inherent advantage in low power for its short range over other wireless communication techniques and occupying the unlicensed Industry Science Medical (ISM) frequency bands. Short range device (SRD) has become an outstanding technique in all sorts of short range wireless communication techniques for its low power and convenience of design. Frequency synthesizer is the key block of SRD transceivers, and this thesis concentrates on the research and design of frequency synthesizers for SRD applications.Firstly, the thesis analyzes various kinds of performance parameters of the frequency synthesizer and defines its specifications according to typical SRD standard ETSI EN330200. Moreover, the thesis analyzes the phase noise of the fractional-N frequency synthesizer and builds up the relationship between loop phase noise and the noise of each block in the loop. What’s more, the thesis addresses how to improve the performance of phase noise for the system.Secondly, the thesis analyzes the non-ideality factor of the charge pumps, VCO and dividers, which are the three main analog blocks in the frequency synthesizer, and their effects on the performance of p11.Thirdly, the thesis studies the block of adaptive frequency calibration(AFC) techniques. And then a high-frequency-resolution and high-speed AFC system is proposed in order to meet the demands of frequency-resolution and the lock time of the system.Finally, the thesis implements a900MHz Sigma-Delta Fractional-N frequency synthesizer with AFC for SRD applications. A digital controlled capacitor array and lowpass filter techniques have been adopted in VCO to improve the phase noise, and a phase selecting prescaler has been used in the divider to implement4/4.5double module divider; What’s more, a low static mismatch structure has been adopted in the charge pump and a high-frequency-resolution and high speed AFC system is implemented. The synthesizer has been fabricated in typical0.13-um CMOS process and the simulation results meet all the requirements.
Keywords/Search Tags:Short Range Device(SRD), Adaptive Frequency Calibration(AFC), Fractional-N Frequency Synthesizer, Phase Locked Loop(PLL), Phase Noise, VoltageControlled Oscillator(VCO), Prescaler, a low static mismatch charge pumps
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