Phase-locked Loop Frequency Analysis Of Co-divider Design Loop

Nowadays ,with the development of modern technology, the demand to the signal is more and more difficult, including the band-width, frequency distinguish ability ,frequency stability, phase noise and low stray, programmable etc. Frequency synthesized technology is the main method of producing many high quality and precise signals. Frequency synthesizer is a phase locked set, and is the very important composed parts of communication, radar, instrument, high speed computer and guidance equipment.The frequency synthesizer is an important RF front-end part in wireless communication. The frequency synthesizer is a PLL(Phase Locked Loop) in GHz range. The PLL in GHz range is one of the highest power dissipation parts in system. So the decrease of PLL power dissipation will have great effect on the whole system power dissipation. The fractional-N frequency synthesizers is a new technology, and has high frequency distinguish ability and low phase noise .The Prescaler(PS) is a feedback block in high frequency PLL. The PS is one of the great power dissipation parts in PLL. So low power dissipation PS is important to the PLL.Firstly, the part 2 introduces the fundamental structure of PLL, and analyzes the linear mathematic models in the locked statement and the response of frequency domain and time domain. The part 3 describes a PLL frequency synthesizer with improved differential preamplifier (with input match circuit) and Prescaler (with CML architecture). I had finished the circuit and layout design. The measured results show locked range is 40MHz-1300MHz, the phase noise can reach -124.60dBc/ Hz at 100 kHz offset whiles the FM Deviation 22Hz for the improved topology and satisfy the specifications. The lock time is 35ms. Secondly, the paper describes the design of a CMOS Fractional—N synthesizer with 3^rd order modulator and programmable Prescaler with division factor64-127. It has been implemented in 0.35μm CMOS process. The simulation results show that the max input frequency is 1.6GHz, the phase noise can reach -144.09dBc/Hz at 100 kHz offset and the power dissipation is 30mW, which satisfy the design demand.At last, the basic designed procedure of this PLL is simply presented and paper shows the other parts used in this design and the results by the test.