The Design And Implementation Of A 900MHz Delta-sigma Fractional-N Frequency Synthesizers

Frequency synthesizer as a high-speed serial communication and radio frequency radio transceiver in the important unit module,its main role is to generate the wireless transceiver for the upper and lower frequency conversion of the local oscillator signal.The local oscillator signal determines the frequency conversion signal of the transceiver,the ideal degree of the local oscillator signal determines the performance of the transceiver.The frequency synthesizer provides the local oscillator signal for the transceiver system.The spectral purity of the output signal directly determines the frequency stability of the transceiver.The output frequency range directly determines the frequency transceiver range of the transceiver.The frequency accuracy determines the minimum channel width of the transceiver.So the lower spurious,the larger output frequency range and the higher frequency accuracy become the design frequency synthesizer important performance index.This paper designs a Delta-sigma fractional-frequency synthesizer chip with output frequency range of 810 MHz to 950 MHz.Firstly,the frequency synthesizer is modeled on the frequency synthesizer based on Matlab and Simulink tools,including sub-module modeling,open-loop modeling and closed-loop modeling.In modeling the sub-modules,the frequency module,The loop filter module and the voltage-controlled oscillator,the noise model of the frequency synthesizer is added to simulate the actual circuit and the optimized loop parameters are obtained.Then,based on the Cadence Specter design platform,the system-level modeling parameters,Including a frequency discriminator,a charge pump,a loop filter,a voltage controlled oscillator,a programmable divider and a Delta-sigma modulator,in which the Delta-sigma modulator is used for a single module.Finally,the open-loop automatic frequency correction technique is used to add the automatic frequency correction module on the basis of the fractional-frequency phase-locked loop circuit to complete the fast switching of the tuning curve.Compared with the traditional PLL frequency synthesizer,this frequency synthesizer realizes the fast locking of the PLL synthesizer based on the extended output frequency range.In this paper,the frequency synthesizer chip is designed in the GMSC 0.18?m process,and the PCB board is designed according to the high-frequency electronic circuit layout and routing rules.Frequency synthesizer test results are as follows: power consumption 91 mW,channel width 20 MHz,the output frequency range 810MHz-950 MHz,1MHz frequency offset phase noise of-97.8d Bc / Hz@1MHz,frequency switching time is less than 60?s.The final layout area of the chip is 1640?m × 1736?m.