Rf Receiver And Design, Fractional Frequency Synthesizer

Digital TV for terrestrial demands a wide frequency range and high SNR, which brings many challenges for the frequency synthesizer of the RF receivers.Aiming at constant loop bandwidth,automatic frequency control (AFC) and reduction of quantization noise,this dissertation has the following achievements based on theΔΣfractional-N PLL frequency synthesizer.Firstly,the loop parameter and phase noise modeling of the PLL are reviewed.The basic principle ofΔΣfractional-N PLL,ΔΣmodulator architectures and quantization noise are presented.The principle of quantization noise transferring to the phase noise is analyzed.Sedondly,the phase noise models of oscillators are reviewed.The model of linear phase time variant is briefly deduced,and an error of the conclusion is indicated.Two issues including tuning type and supply noise suppression are analyzed.A equivalent model is proposed to extract the impedance of center-tapped differential inductors.In terms of the problem of large variation of loop bandwidth in wideband PLL,two methods are presented,in which the one to keep tuning gain and band step is analyzed in detail.A 1.175GHz～2GHz integer-N PLL is implemented to validate the proposed technique.The measured results show that the variation of loop bandwidth is less than 9%.In terms of the residual fractional error existing in conventional AFC techniques applied in fractional-N PLL,a division-ratio-based AFC technique is proposed.Detail error analysis of the proposed technique is shown.A 975MHz～1960MHz fractional-N PLL is implemented to validate the proposed AFC technique.In terms of the out-of-band phase noise due to the quantization noise of theΔΣmodulator,a 4/4.5 prescaler is proposed to realize a division ratio of 0.5. An endocing method for programmable P/S counter is proposed to obtain wide fractional divison ratio with theΔΣmodulator.Based on the previous theoretical analysis and some techniques,a 1.2GHZ～2.1GHzΔΣfractional-N PLL frequency synthesizer aiming at DVB-T is implemented in a 0.18-μm CMOS process.The chip area is 1.47mm~2 and the power is 25.2 mW.The measured results show that the variation of loop bandwidth is less than 10.7%,the in-band phase noise is -96dBc/Hz,the integrated phase error is less than 0.75°,the reference spur is less than -71dBc/Hz and the locking time is less than 20μs.