Used In Radio Frequency (rf) Wireless Communication System Of Multimode Scores Points Frequency Synthesis Device Design And Research

Wireless communication market is undergoing a transition from2G to3G and at the same time,4G technique is emerging. Thus a multi-mode mobile handset supports all standards is necessary to cater for market’s demands. To design such a system, a high-performance low-cost multi-mode frequency synthesizer is of great importance. In this thesis, a multi-mode wideband low-phase-noise fractional-N EA frequency synthesizer is studied and designed for GSM/WCDMA transceivers.Firstly, the fundamentals and structures of PLL-based frequency synthesizers are introduced. System architecture and specifications are defined according to GSM/WCDMA protocols.Phase noise is one of the most important specs for frequency synthesizers in wireless communication system. GSM has very tough requirement of phase noise, which is the main obstacle to widely spread of CMOS frequency synthesizer. In this thesis, a phase domain model is built, phase noise contributions of different blocks in the system are analyzed and the method of simulating system phase noise is proposed to design and improve phase noise at system level. Moreover, techniques to optimize loop parameters are also introduced. In order to guarantee the stability of designed PLL, an algorithm is proposed to take care of non-ideal factors which can help estimate effects attribute to variations of process, temperature and frequency at system design level.Then, some key building blocks in high-performance multi-mode fractional-N frequency synthesizer design are carefully studied. Voltage controlled oscillator (VCO) is one of the most important blocks because it determines frequency range and out-band phase noise. After a brief introduction of two most commonly used LC VCO structures, techniques focusing on improving wideband VCO’s phase noise are proposed based on phase noise mechanism. Furthermore, fundamentals of Σ-△modulator are introduced, according to which some design considerations are offered and demonstrated. And an optimized design flow for high order Σ-△modulator is concluded. It is known that automatic frequency calibration (AFC) circuit is the indispensable block in frequency synthesizers for wireless communication application. In this thesis, a comparison of digital AFC techniques is given, and then a high-frequency-resolution and high-speed AFC system is proposed.Finally, a prototype is implemented in0.13μm CMOS technology. Experimental results show that the designed1.2V wideband frequency synthesizer is locked from3.05GHz to5.17GHz within30μs. The measured in-band phase noise are-89,-95.5and-101dBc/Hz for3.8GHz,2GHz and948MHz carriers, respectively, and accordingly the out-of-band phase noise are-121,-123,-132dBc/Hz at1MHz offset, which meet the phase noise mask requirements of required standards. The frequency synthesizer described in this thesis is already integrated in multi-mode RF transceivers.