Research On Digital Calibration Algorithm Of Pipelined ADC/Pipelined-SAR ADC Based On Metastability Detection

Analog-to-Digital Converter(ADC)is an exchange window for analog and digital information,and it occupies an important position in the contemporary communication field.However,due to the significant non-ideal effects caused by the proportional reduction of component size,the instability of the application environment,the change of circuit parameters,and the influence of many factors such as limited open-loop gain and limited bandwidth in actual circuit design,the actual performance parameters of ADC are different from the original There will be a certain deviation in the setting index.In order to optimize ADC performance,calibration technology is introduced in the circuit design to improve its quantization accuracy.Among them,digital background calibration technology that can follow error changes in real time and update calibration parameters is widely used by designers.This article is mainly based on the mechanism of metastable detection technology to calibrate the gain error and capacitance mismatch error of the traditional pipelined ADC and pipelined-successive approximation analog-to-digital converter(Pipelined-SAR ADC)of the pipeline architecture Design implementation and simulation verification of calibration algorithm.First,analyze the sources of errors in the Pipelined ADC and Pipelined-SAR ADC circuits,and then summarize and establish a unified error model based on the similarity of the Pipelined ADC and Pipelined-SAR ADC architectures.Then according to the metastable mechanism of the comparator,the basic principle and calculation formula of the error coefficient are explained,and the specific realization method of the circuit is explained respectively.This article applies the proposed gain calibration scheme and capacitance mismatch calibration scheme based on metastability detection in a 14-bit Pipelined-SAR ADC.First,use Python language to compile the ADC error model and calibration algorithm and perform behavioral-level simulation.Through Monte Carlo randomization of the error coefficients,the statistical results of the final output of the FFT analysis are used as the standard to measure the performance and stability of the calibration algorithm.Then the Verilog language is used to implement the algorithm hardware logic circuit,and the logic circuit is simulated on the Modelsim platform to verify the consistency of its logic functions.RTL-level calibration simulation results show that this algorithm increases the SNDR of a Pipelined-SAR ADC with a specific error coefficient from 56.57 d B to83.23 d B,and the SFDR from 67.57 d B to 100.65 d B.From the comparison of the results before and after calibration,it can be seen that this calibration algorithm has a good calibration effect and greatly improves the overall performance of the ADC.