Design Of MDAC In 14Bit 125MS/s Pipelined ADC

With the fast development of modern wireless communication systems, high speed and high resolution analog-to-digital converters (ADCs) has been widely researched recently. Pipelined ADCs are appropriate choices for high speed and high resolution ADCs because of the good performance in speed, resolution and power consumption.This thesis designed a Multiplying Digital-to-Analog Converter(MDAC),which is a crucial module in a 14bit 125MS/s pipelined ADC. Different kinds of ADCs are compared briefly, and the structural advantages of pipelined ADCs in realizing both high speed and high resolution are analyzed. The Simulink models of nonideal error sources in pipelined ADCs and the power consumption estimation model are created, the systematic design is done with the help of the models, and the resolution of the first stage is chose to be 2.5bit. A fully differentiate capacitor flipped switched-capacitor circuit is used as the basic architecture of the MDAC to reduce the area of the circuit and improve the feedback coefficient. A kind of charge pump reused bootstrapped switch is designed to reduce the sampling switches' on resistance and its nonlinearity. Gain-boost technology and Ahuja compensation are used to improve the gain, bandwidth and stability of the two-stage differentiate amplifier. What's more, a novel digital calibration circuit is designed to reduce the nonideal influence of capacitor mismatch. And this circuit is characterized by small area, low power consumption and fast calibration.The schematic and layout of the MDAC are designed in SMIC 0.181P6M CMOS Process. The post-simulation shows that 74.51dB SINAD and 85.29dB SFDR are achieved under the condition of 1.8V voltage supply,125MHz sampling rate, and 14.892578125MHz, ±780mV sine signal. The total consumed current is 39.9mA. All of the design specifications are fully met.