Research On Nano-scale High Resolution Pipelined Successive Approximation Register Analog-to-digital Converter

The analog-to-digital converter(ADC)is used as an exchange interface between analog and digital signals,and its application scenarios and demand are increasing day by day in recent years.5G technology has become popular in recent years,and its requirements for ADC performance are higher than before.ADCs in communication base stations need to have both high spurious-free dynamic range(SFDR)and signal-to-noise distortion ratio(SNDR).Pipeline ADC is the preferred structure for high speed and high resolution ADC.However,in the 5G era,equipment amount has increased exponentially,and the high power consumption characteristics of pipeline ADCs limit its application prospects.The feature size of the process is 5nm now,and the successive approximation register(SAR)ADC,which is more popular with advanced technology,has been greatly developed in recent years.However,due to the nature of the binary search algorithm,its working mode is serial operation,and each sampling cycle needs to include multiple comparison cycles.Therefore,high-resolution SAR ADCs have strict requirements on sampling switches,comparators,and unit capacitors.The Pipelined-SAR ADC combines the above two ADCs perfectly inherits the advantages.The two-stage structure greatly improves the speed of the SAR ADC,and the amplifier relax the requirement for the comparator.This structure is very suitable for high resolution ADCs.This thesis is dedicated to the research of the system architecture and key modules of the high-resolution Pipelined-SAR ADC.In this thesis,the basic structure and key modules of the high-resolution Pipelined-SAR ADC are studied,which mainly include comparator and dynamic amplifier.At the same time,the redundancy calibration for SAR ADC and the inter-stage redundancy bit calibration for Pipelined-SAR ADC are studied.The meaning of the bit weight of the ADC and the inherent reason why the redundant bits can be superimposed are analyzed in detail.An 11-bit 100MS/s Pipelined-SAR ADC is proposed in this thesis.A comparator reused as amplifier is proposed.The comparator of the first-stage SAR ADC is time-multiplexed,used as a comparator when the first-stage SAR ADC is quantizing,and used as an inter-stage amplifier in the phase of the residue voltage amplification.At the same time,the PVT stabilization module is used to improve the robustness of the amplifier gain.The module uses a single-pole amplifier and the V2T module to make the gain expression of the dynamic amplifier as a ratio to realize the stabilization.An improved structure of the bootstrap switch is proposed,and the propagation delay of the input clock is reduced by removing the redundant transistors to speed up the speed.The chip is fabricated in the TSMC 65nm process.The simulation results show that the SFDR is 79.3d B,SNDR is 66.3d B,and ENOB is 10.71 bit at a sampling rate of 100MS/s and Nyquist input frequency.The chip area is0.17mm~2.The measurement results show that DNL and INL are–0.79/+0.91 LSB and–1.01/+0.73 LSB,respectively.At 100MS/s sampling frequency and Nyquist input frequency,the SNDR is 60.7d B,SFDR is 70.5d B,ENOB is 9.78 bit,and power consumption is 2.12m W making a 23.7f J/c.s of Fo M_W.A 14-bit 180MS/s Pipelined-SAR ADC is proposed in this thesis.By studying the nonlinearity source of the dynamic amplifier,adaptive region selection(ARS)technique is proposed.This technique is equivalent to using multiple amplifiers to amplify the input signal in different regions to improve the linearity of the overall dynamic amplifier.Matlab is used to model this technique,detailed implementation scheme is studied,and the impact of its error on the performance of ADC is analyzed.The first-stage SAR ADC uses the Coarse-fine structure to optimize the speed and power at the same time,and is perfectly compatible with the ARS technique.The comparator and the dynamic amplifier are studied,and a clock circuit with low jitter and adjustable sampling time is realized.At the same time,adding the inter-stage offset calibration capacitor,combined with the inter-stage offset voltage background detection technique,can eliminate the offset voltage difference of the first-stage sub-ADC comparator,dynamic amplifier and the second-stage sub-ADC comparator.The post simulation results show that by using the adaptive region selection technique,73.8d B SNDR and 87.2d B SFDR are achieved at a sampling rate of 200MS/s.The chip is fabricated in TSMC 28nm process and the ADC core area is 0.023 mm~2.The measurement result shows that the ARS technique improves the SNDR by 7.92d B to70.61d B,and the SFDR also reaches 81.75d B.The DNL and INL are-0.44/0.45 LSB and-1.94/1.98 LSB,respectively.The ADC consumes 1.3m W from 1V supply with 180MS/s.The Walden and Schreier Fo Ms are 2.6 f J/conversion-step and 179 d B,respectively.