Research And Design Of 14bit 100MSPS Pipelined SAR Analog-to-Digital Converter

As a medium for converting analog signal to digital signal,ADC?analog-to-digital converter?is the interface between the physical world and the digital world.With the advent of 5G era and the rise of autonomous intelligent equipment,the analogy and digital mixed-signal chip of the whole machine has put forward higher requirements on the speed,accuracy and power consumption of ADC.In the field of high-speed and high-resolution ADC,pipelined ADC has always occupied a dominant position.However,with the decrease of process size and power supply voltage,the design of internal MDAC becomes more and more difficult,and the power consumption efficiency is difficult to improve.With the features of high digitization,low power consumption and strong compatibility,successive approximation ADC provides a new idea for the design of analog-to-digital converter.Analog-to-digital converter is no longer limited to a single structure,and many hybrid structures based on successive approximation ADC are invented.Pipelined successive approximation ADC as a typical representative of hybrid structure has become a research hotspot.In this paper,a 14-bit100MSPS Pipelined SAR ADC is designed with the hybrid ADC architecture in the40nm CMOS process.The paper adopts the design concept of top-down,analyzes the influence of Pipelined series and precision on speed and power consumption according to the Pipelined SAR ADC structure and working characteristics combining with matlab modeling and proposes the distribution scheme of system architecture of 6_?1?+9.The paper studies the characteristics and main structure of dynamic residue amplifier;The optimal design of pipelined sar ADC internal timing is carried out that the inter-stage asynchronous timing and intra-stage asynchronous timing are adopted to reduce time waste.The paper studies and designs the key modules,the interstage is applied by redundant technology,and the nonbinary weighted capacitor array is used in the stage to provide redundancy to reduce building speed requirements.What's more,the first-stage DAC applies the Vcm-based switching method to reduce power consumption,enhancing linearity,the second-stage DAC uses traditional switching way with reset,reducing the residue amplifier reset time;The gain requirement of residue amplifier is reduced by interstage attenuation technology,a steady-gain dynamic residue amplifier based on common mode voltage detection is designed,and some analog methods are used for PVT compensation to reduce the gain variation.In order to avoid the offset of the first-stage comparator exceeding the redundancy range,a offset self-correcting circuit based on the charge pump was designed.The offset voltage of comparator is reduced in a short time by the self-correction operation.In this paper,the circuit and layout design are completed in 40nm CMOS process,and the circuit is simulated by Hspice.The simulation result of Hspice shows that under1.2 V power supply voltage,when the sampling rate is 100 MS/s,the input signal frequency is 47.65 MHz,signal amplitude is-1dB of full scale sine signal,the Spurious Free Dynamic Ratio?SFDR?is 88.52 dB,the Signal-to-Noise and Distortion Ratio?SNDR?is 78.51 dB,the Effective Number of Bits?ENOB?is 12.75 bits,the power consumption is 5.64 mW,the FOM value is 8.2 fJ/Conversion-step,the core circuit area is only 0.0683mm²,Its performance index can meet the requirement of design index.