Research And Design Of 14-bit High Speed Pipeline_SAR Analog Digital Converter

The development of the semiconductor industry is changing with each passing day.The constant shortening of the channel length has deviated from the once Moore's law.On this basis,the chip area is also reduced,and the power supply voltage of the circuit is greatly reduced.The demand for the performance of the circuits is increasing,and the high performance circuit design has brought great challenges to the designers.The constant innovation of the structure and the tradeoff that is more compatible with the application environment will be one of the designers' choice.Based on the development of today's industry,this paper has designed a pipelined successive approximation analog to digital converter(Pipeline_SAR ADC)with a precision of 14 bits.Compared to the traditional analog to digital converter structure,this design has made an innovation in the structure and make full use of the advantages of various circuits and combining them.The design and Simulation of the circuit have been completed under the 40 nm process.First of all,Matlab modeling for this novel structure fully validates the effectiveness and rationality of pipelined successive approximation structure,and determines the basic structure of the 14 bit Pipeline_SAR ADC designed in this paper through a large number of data comparison.The two level pipeline structure is adopted in the design.The sub ADC of each level is composed of SAR ADC.The first level is designed as 6 bit precision,the second level is 9 bit precision,and the overall 14 bit effective accuracy is achieved through the redundancy between two levels.In addition,the key module of the anolog and the key module of the digital are optimized.The design of the layout is completed and the overall simulation of the system is completed.Secondly,in order to reduce the overall power consumption of the circuit,the amplifier of the residual voltage between the two sub ADC use a novel structure.This structure is used in open-loop conditions,compared with closed loop applications,which can greatly reduce the power consumption of the amplifier.Besides,the amplifier with this structure can achieve better linearity under the condition that the amplification factor is not high and its amplification time is short,and it does not vary with the amplitude of input signal.Ultimately,under the condition of 111.11 MHz sampling frequency,19.96 MHz input signal frequency,results show that the spurious free dynamic range(SFDR)of the ADC is 81.548 dB,the SNDR is 75.972 dB,the effective number of bits(ENOB)is 12.408 bit.The power consumption of the circuit is 6.87 mW.