Design Of 10bit 40MHz Pipelined Analog-to-Digital Converter

The pipelined analog-to-digital converter(ADC) is a popular structure in both application and research for its high-speed and high-resolution data conversion. Furthermore, the pipelined ADC needs less number of comparator, so the area and the power dissipation can be decreased.The pipelined ADC includes not only analog parts such as the sample and hold circuit, the multiplying DAC, the dynamic latch comparator, the operation amplifier and the bandgap voltage reference, but also digital parts such as the register, the multiplexer and the clock generator. So the design of this type of converter is mixed signal design. Since this type of converter has little requirement for the digital parts and its digital structure is relative simple, the design approach of the digital circuit is the same as the analog circuit does.For circuit design, the thesis mainly introduces the unit circuit of the pipelined ADC. The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through. A type of dynamic voltage comparator which is no DC power dissipation is used in every stage to improve speed and decrease power. The gain-boosted folded cascade architecture is used to ensure the opamp has a very high dc gain together along with a high unity-gain bandwidth and low power dissipation. The key cells of ADC which are 3.3V power supply have been simulated in 0.18um CMOS technology with the parameter model of SMICV1P5 by HSPICE.By the simulation result, all the parameters can be satisfied with the design specification in the corner of TT, but the noise of circuit is increasing so much in the corner of SS that degrades the performance of the pipelined ADC. So how to decrease the circuit noise in SS is our further work. Now the chip have been tape-out and is prepared to be test.