Research On Key Technologies Of 14-bit High-speed Pipelined Successive Approximation Analog-to-digital Converter

As the bridge between analog signal and digital signal,the analog-to-digital converter(ADC)has a great effect on the performance of communication and intelligent sensor systems,and has been a research hotspot in the field of analog integrated circuits for a longtime.Pipelined analog-to-digital converter(ADC)is the first choice to achieve high speed and high precision because of its pipelined operation.However,because the traditional structure contains a large number of operational amplifiers and comparators,the power consumption increases greatly with the increase of precision.In comparison,the SAR ADC has obvious advantages of energy efficiency,simple structure and high compatibility with advanced process.However,its speed is limited by the number of comparisons and the speed of comparator,and its accuracy is limited by the input noise of comparator.Based on the advantages and disadvantages of the two kinds of ADCs,the hybrid Pipelined SAR ADC provides a good solution for the realization of high speed and high precision ADC under advanced process.This hybrid structure not only retains characteristics of low power consumption of SAR ADC,but also utilizes pipelining technology to achieve high precision and high speed.This thesis first introduces the principle and infrastructure of the Pipelined SAR ADC.Considering that the SAR ADC is an important module of the ADC system,its core circuits including sampling switch,DAC switching scheme,comparator and SAR dynamic logic are studied in this paper.Then the thesis focuses on the analysis of the Multiplying DAC(MDAC)circuit based on the traditional operational amplifier.On this basis,this thesis adopts the gain-enhanced dynamic amplifier utilizing bypass current as a new type of residue amplifier,which can greatly improve the amplification gain and effectively reduce the overall power consumption,area and design complexity of ADC.Because the dynamic amplifier is similar to the open loop application of the op-amp,its gain is affected by the input,so the linearity is poor.In order to improve the linearity of the module of residue amplification,this thesis proposes a system solution of residue folding,which can improve the spurious-free dynamic range(SFDR)of the overall ADC without optimizing the dynamic amplifier structure.At the same time,Subrange DAC structure and Floated Detect-And-Skip(FDAS)capacitor array switching algorithm were used to further optimize the speed,power consumption and linearity of the first stage ADC.In this thesis,the system modeling and verification of the Pipelined SAR ADC using the residue folding technology are carried out by using MATLAB.In addition,the paper also analyzes and simulates the non-ideal factors of the Pipelined SAR ADC based on the dynamic amplifier in MATLAB.Based on TSMC 65nm CMOS process,this thesis designs a 14-bit 50MHz Pipelined SAR ADC with 1.2V power supply voltage and configurable working mode.The post-layout simulation results show that when the input signal frequency is 24.5605MHz and the input swing is 2.4V_PP,the output results of folding mode can achieves measured SFDR,SNDR and ENOB of 95.0d B,72.8d B,and 11.80 bits.The total power consumption of the circuit is1.92 m W,and the core area of the ADC is 0.186mm².