High-speed And Low-power Research On Pipelined-SAR ADC

Analog-to-digital converter(ADC)is an important module of communication systems.The function of ADCs is to convert analog signals in the nature into digital signals.In recent years,the rapid development of wireless communication,computers,wearable devices and on-board electronics has put forward high-speed and low-power requirements for ADCs.Among all of the ADC structures,high-speed conversion can be achieved by time-interleaving,flash and pipeline architectures,but the power consumption of these structures is very high.Low power conversion can be realized by the successive approximation structure,which has the advantage of small area and low power,but the speed is limited by its resolution.The Pipelined-SAR ADC which is proposed in recent years,has outstanding performance in single channel converters.It can realize the requirements of high-speed and low-power at the same time.Pipelined-SAR ADC usually consists of two stages and a interstage amplifier.It utilizes SAR structure as sub-ADC,which can not only achieve higher resolution at the first stage,thus improve system performance,but also has CDAC in SAR structure,so MDAC does not need to be designed separately.There are two difficulties in the design of Pipelined-SAR ADC,one is how to transfer the residual voltage accurately,the other is the design of high performance interstage amplifier.This paper optimized the residual voltage transfer method and timing of Pipelined-SAR ADC,aiming to improve the sampling rate.Variable resistor-based self-biasing ring amplifier is used as interstage amplifier to improve the bandwidth of amplification stage.A 12bit 200MS/s Pipelined-SAR ADC is designed and simulated based on 40nm TSMC 1P6M CMOS technology.The two sub-ADCs utilize traditional SAR logic and monotonic SAR logic,respectively.The pseudo-differential resistor-based self-biasing ring amplifier is used as interstage Amplifier.With an input frequency of 20MHz,input amplitude of 1.1V,and sampling rate of 200MS/s,the layout simulation SFDR is69.17dB,SNDR is 56.54dB,power consumption is 4.14mw,and FoM_W is37.72fJ/conv-step.