Research And Design Of 8-bit High-Speed Folding And Interpolating A/D Converter

High-speed signal processing applications such as wireless network, information and communication system are increasing high requirement of speed and accuracy of the ADC. Folding and interpolating ADC inherits high speed characteristic of the Flash ADC, and it can greatly reduce the number of the comparator with coarse and fine quantification process working in the same time. So, folding and interpolating ADC will be the hot spot of high speed ADC because of reducing the system size and power consumption. Designing a high performance folding and interpolation ADC has important theoretical significance and practical value of application.This paper introduces the principle of folding and interpolating ADC firstly, then it explains how the coarse quantification channel and fine quantification channel work synchronously, and illustrates the basic principle and circuit structure of technology of folding and interpolating in details. For comprehensive consideration of the system speed, resolution, area, power consumption, this design finally adopts 3-bit coarse quantification and 5-bit fine quantification structure, and selects differential pairs folding and voltage interpolating architecture. Secondly, this paper takes two-stage cascaded structure to alleviate the impact of the non-ideal effects through analyzing non-ideal factors existing in the traditional single-stage folding and interpolating ADC and giving corresponding solutions. According to the ideal system-level model, it validates the feasibility of the two-stage cascaded structure. On the basis of the ideal model, this paper shows how the parameter of key modules influence the performance of the whole system, then to guide the actual circuit design process. Finally, on the basis of the principle analysis and system-level model, some key circuits of folding and interpolating ADC are designed and simulated, including front-end pre-amplifiers, folding circuit, interpolating circuit, comparator, and so on. The load effect of pre-amplifiers for reference voltage resistance network is also analyzed. Using 3*3 cascaded folding circuit can achieve large folding coefficient, while the bandwidth requirement of folding circuit is effectively reduced. By using two-stage small interpolating coefficient of resistance interpolation structure, it can improve the problem of zero-crossing offset, so as to improve the linearity of the system. Bit synchronization circuit ensures the coarse and fine quantification signals to export synchronously, to eliminate the occurrence of error codes.Based on TSMC 0.18um CMOS process and the power supply voltage of 1.8V, the designed circuit is simulated under the Cadence Spectre environment. The simulation results show that when the sampling frequency is 500MHz and the frequency of input sinusoidal signal is 7.8125MHz, the ENOB is 7.50bits. When the sampling frequency is 1GHz and the frequency of input sinusoidal signal is 465.82MHz, the ENOB is 7.26bits, meeting the requirement of design index.