Research And Design Of Low Power Techniques Of High Speed Pipelined-SAR ADC

In the physical world,the signals we can observe are all analog signals.As an easyto-understand continuous signal,the analog signal must be converted into a binary digital signal when it needs to be stored and transmitted in an electronic device.Therefore,we can say that the analog-to-digital converter is a bridge connecting the physical world and the virtual electronic world.Due to the complex structure of the analog-to-digital converter and the numerous modules,it often becomes one of the designers' focus in the design of integrated circuits.In recent years,with the popularization of 5G,people's demand for high bandwidth and high bit rate has become stronger.However,under the premise that the battery technology of portable devices(such as smart phones and tablet computers)has not been greatly improved,achieving higher signal processing and transmission rates with lower power consumption has become a hot topic of the research and development of industry and academia.Two-step Pipelined-SAR ADC is a widely used high-speed and low-power analogto-digital converter solution today.It combines the advantages of high digitization and low power consumption of SAR ADCs,and the advantages of Pipelined ADCs that are easy to achieve higher bandwidth.It's a typical hybrid architecture ADC.This article aims at the traditional Pipelined-SAR ADC,analyzes its system power consumption that can still be optimized,and points out that optimizing the structure and timing of the residue amplifier can further reduce the system power consumption.Based on this idea,this paper designs a two-step Pipelined-SAR ADC based on an open-loop amplifier with high linearity and low power consumption.The proposed method is verified through MATLAB-based system behavioral modeling and Cadence Virtuoso-based circuit design simulation.This design is based on a 28 nm CMOS process,and achieves a 500MS/s sampling rate and 12-bit accuracy under a 0.9V power supply voltage.When the full amplitude signal of Nyquist frequency is input to the system,the SINAD realized by the system is 63.88 d B,SNR is 64.63 d B,SFDR is 75.40 d B,and the ENOB is 10.32 bits through calculation.