Design Of 7bit 16MS/s Low Power Consumption Pipelined ADC

With the development of modern wireless communication, Bluetooth, WiFi and Zigbee technologies have bottlenecks to overcome in terms of low power consumption. As its key modules, low power ADC can reduce its system power consumption and become a research focus.In this thesis, a 7bit resolution 16MHz sample frequency low power consumption pipelined ADC is designed for the application of Bluetooth Transceiver. Non-ideal error source of pipelined ADC is analyzed in detail,and a low power consumption pipeline ADC is designed. On the system architecture, embedded SHA and OTA sharing technique are adopted to save power dissipation with the use of polarity reversal method to reduce the memory effect of OTA sharing. Meanwhile, the power consumption module is created to optimize the single-stage resolution. In the circuit module design, dynamic comparator and class-AB buffer to reduce power consumption with the adoption of redundant bit correction technique to ease restrictions of comparator offset. As the core of the pipeline ADC module,OTA affects the performance of the whole system directly. Therefore, a OTA design procedure is presented in detail, including the determination of the OTA specification,the selection of circuit architecture and the method of common mode feedback and so on.The chip is fabricated in SMIC 0.18?m single-poly six metal mixed-signal CMOS process,and the die area is 0.29mm2 with 1.8V supply voltage. The chip-test is carried out at 16MHz sampling frequency, with an input frequency and amplitude of 0.4375MHz and 600mV of a sine wave signal. The ADC achieves a SFDR of 41.6dB and a SNR of 36.6dB, and the ENOB is 5.38bit and the power consumption is 4.8mW in testing module,which meets the system design requirements.