Design Of 12 Bit High Speed Low Power Consumption Pipelined ADC Based On 55nm Technology

Benefit from the fast development of communication and consumer electronics, SOC, system on a chip, is widely used. Now, with portable electronics coming deeply into people’s life, the functions concentrated into SOC are much more complicated and powerful. So the IC with lower consumption and advanced performance is becoming a hot study. It is all known that the feature size of CMOS technology is decreasing quickly in recent years. This leads to larger eigen frequency, lower consumption and higher integrity of MOS, however, lower intrinsic gain and power supply at the same time, which makes IC design much more difficult. It is so as to the ADC, critical module connect analog circuit with digital one. It is now a challenge to design a lower consumption and higher performance ADC used in SOC under advanced process for analog IC designer.This work designed a low power consumption 12 bit, 160M/s, more than 11 bit pipelined ADC. First, this dissertation analyzes important parameter of ADC and sources of non-ideality. Then, common techniques reducing power consumption are introduced. After compared, amplifier sharing, nesting gain boosting amplifier, scaling down are chosen. According to those, systematic analyses, arrange and design of pipelined ADC are done. Finally, specific circuits design are finished. It is indicated by the post layout simulation that with 160M/s sampling rate, 39.1MHzsinusoidal input signal, this pipelined ADC has a 83.05 dB SFDR,72.1dB SNDR,11.68 bit ENOB with only 54 mW power consumption, which is satisfied with video AFE system requirement.All the work presented in this paper are finished based on nano technology. They have a good reference value in mix signal circuit design and layout. Because of invest-igation in low power consumption design, it is good for people designing low power consumption function in SOC.